Do you have measurements of the phase noise floor for the divide by 2 and divide by 16 outputs for HMC739?
Please note I am interested in the phase noise floor, not the phase noise when free-running VCO is divided by 2 or 16, as this will be dominated by the VCO noise close to carrier.
For example if the div-by-16 divider noise floor is -130dBc/Hz at a particular offset then phase locked, the VCO can only ever be as good as -130 + 20*log(16) = 106dBc/Hz, even if the phase detector and reference are substantially better.
If it is not possible to provide measured data, can the performance be inferred from a similar part? If so, what VCO or divider IC please?