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HMC832

Hi,

I'm using the HMC832 in the conditions fixed in the datasheet p34 figure 52 (loop filter design).

We choose the loop filter type 1 in the table12. The Fxtal is 40Mhz.

Depending of the output frequency desired, the HMC832 declares an unlock condition or not.

I noticed that the PLL was locked when the fvco (=k*fout) was high, close to the 3000Mhz.

For example :

  • fout = 500Mhz, k=6, Nint=75 et Nfrac=0 (Registre3=75, Registre4=0) -> the PLL is locked
  • fout = 500,1Mhz, k=4, Nint=50 et Nfrac=0.01 (Registre3=50, Registre4=167772) -> the PLL is unlocked
  • until fout = 629.4Mhz, k=4, Nint=62 et Nfrac=0.93999996 (Registre3=62, Registre4=15770584) -> the PLL is unlocked
  • from fout = 629.5Mhz, k=4, Nint=62 et Nfrac=0.95000400 (Registre3=62, Registre4=15938422) -> the PLL is lockedto fout = 750Mhz, the PLL is locked.

I configure only the registers not used with default value:

REG1 0x3

REG7 0x214D

REG9 0x603264

REG5 0xB238

REG5 0x5D98

REG5 0

And then, each time I configure a new frequency:

REG5 XXXX with the k value

REG5 0

REG3 and REG4 with the new value

What do you think of my initialization ?

Thanks.

Regards

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  • Hi,

    Your initialization and update sequence looks correct. REG6 should be updated to a different value (0xF4A) than the default. Can you add that? It is better to write all registers. You can use the register file given in the GUI package as a reference.

    Can you please confirm..
     this is your own board, not the eval board?
     the PLL is really not locking rather than just the lock detect fails?

    Is it possible to check the PN profile to confirm there is no issue with the loop filter, no peaking?

    What is changing when transitioning from 250MHz to 250.1MHz? Does VCO jumps from 3000MHz to 1500MHz for the first time?

    Regards,
    Kazim

  • Hi,

    Thanks for your answer, it helps.

    I list all the registers left with default value. I updated REG6 with 0xF4A and REGA with 0x85.

    Now, the PLL is always locked.

    In the register 0x0A, I wonder why the default value of bit 9:3 is 64 instead of 8 as it is specified in the description ?

    Regards

  • Hi,

    It is great to hear the problem is solved.

    Are you asking in a general manner or specific to register 0x0A?

    Those bits are used to optimize the autocalibration process. The default (hard-coded) value is expected to be the best choice in design stage (by simulation). But when testing the part, another value is found that gives better results, or even the default value may fail at all. In this case a new value different than default is recommended. Is that what you are asking?

    Regards,

    Kazim

  • Hi

    Yes, I was asking in a general manner.

    I understand what you mean. Thanks for these explanations.

    Regards

  • Hi,

    I meet another problem with the HMC832.

    I succeed in programming the module correctly and it is always locked but for some frequencies it is not

    exactly locked at the right frequency.

    For example, at 80Mhz the output is 81.5Mhz.

    We use an Xtal=40Mhz and we noticed that it happened at 40/80/160Mhz.

    Thanks for your help.

    Regards

    Christine

  • Hi,

    Can you help me about my problem  ?

    Do you know why the output frequency is shifted when I program 40Mhz or 80 Mhz or 160Mhz ?

    Thanks.

    Regards

    Christine

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