Question about EVAL-ADF4159

Hello,

My customer ask some questions about function of REFIN SMA connector.

She wants to use this connector as other purpose.

Would you confirm below questions and share your opinions?

Please refer below questions and let me know your opinions.

Regards,

Se-woong

Parents
  • +1
    •  Analog Employees 
    on Feb 9, 2021 10:36 AM 1 month ago

    Hi, The REFIN SMA is intended to be an input, but I think the configuration you have proposed might work in getting two boards to lock with one on-board reference - but I haven't tried it myself. You might need to change R10 to 0ohm for enough signal power.

    Note, the ADF4159s sharing the same reference in this way likely would not be phase synchronized. I am not sure the REFIN trace lengths are equal enough - it would be better to use an external reference equally split with equal length cables. To achieve phase coherence in integer mode you would need a way of ensuring the LE of the SPI writes to each part happens at the same time to ensure the counters of all PLLs are taken out of reset at the same time. This ensures all PLLs are running at the same divider count in relation to REFIN and thus will be in phase. To keep multiple parts in phase in fractional mode it is not so straightforward. See below link for more information

    https://ez.analog.com/rf/f/q-a/75753/adf4350-phase-resync

    Alex

Reply
  • +1
    •  Analog Employees 
    on Feb 9, 2021 10:36 AM 1 month ago

    Hi, The REFIN SMA is intended to be an input, but I think the configuration you have proposed might work in getting two boards to lock with one on-board reference - but I haven't tried it myself. You might need to change R10 to 0ohm for enough signal power.

    Note, the ADF4159s sharing the same reference in this way likely would not be phase synchronized. I am not sure the REFIN trace lengths are equal enough - it would be better to use an external reference equally split with equal length cables. To achieve phase coherence in integer mode you would need a way of ensuring the LE of the SPI writes to each part happens at the same time to ensure the counters of all PLLs are taken out of reset at the same time. This ensures all PLLs are running at the same divider count in relation to REFIN and thus will be in phase. To keep multiple parts in phase in fractional mode it is not so straightforward. See below link for more information

    https://ez.analog.com/rf/f/q-a/75753/adf4350-phase-resync

    Alex

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