ADF4002 device programming with an FPGA

Yes, we normally use FPGA-SPI interface for setting PLL device. Check the logic compatibility & clock frequency and add suitable serial resistors (or EMI filters) in case you want to reduce interference risk. 

Thank you for your response. I guess this means I have to program a certain logic to serially send 4 x 24 bit data to the ADF4002 along with the clock and enable signals. I am asking this because I have to design and order the pcb  before I experiment on the device's behavior of operation. Also curious, is there any radiation hardened version for such charge pump ICs ?

Mikias said:

Also curious, is there any radiation hardened version for such charge pump ICs ?

I never seen this PLL chip variant with this feature.

Hi, Yep as Viktor said check the timing diagram in the datasheet for timing characteristics. Most FPGAs should be able to handle the timing requirements of the ADF4002 no problem. 

Currently the only space qualified PLL we have is the ADF4108S
https://www.analog.com/en/products/adf4108s.html#product-documentation

Regards,

Alex

Hi, Yep as Viktor said check the timing diagram in the datasheet for timing characteristics. Most FPGAs should be able to handle the timing requirements of the ADF4002 no problem. 

Currently the only space qualified PLL we have is the ADF4108S
https://www.analog.com/en/products/adf4108s.html#product-documentation

Regards,

Alex