AD8302 signal at VPHS phase detector output of same frequency as input signal


I put the AD8302 on a board of my own design. I purchased an AD8302 eval board that will be coming soon.

I am getting at the VPHS output a 5MHz signal of the same frequency as the 5MHz I apply to both inputs. I like some help. What is the normal operation of the phase detector XOR circuitry and filtering settings??

I made a test with a 5 MHz -30dB generator going to a splitter. On one side, I put a very long cable to get a phase difference.  I made the PCB with a low pass1k 4700pF RC filter to get 33kHz BW. In my final application, I will have the phases difference changing in time with a BW below 24kHz. Just for now, I keep the phase difference constant.

I made a capture below with the blue channel at  VPHS and the yellow after R6 C9. I get 1.47Vpp at VPHS and 12mVpp after the low pass filter. I did not use C8 at PFLT. Was the usage of C8 the main idea to convert the digital XOR output into an analog value? Is the circled X in the below drawing the XOR?

So with the formula at page 16, do I just use T (ns) = 3.3 × CAVE (pF). where I put T my time constant for 1/24kHz = 41000ns ?



  • 0
    •  Analog Employees 
    on Jan 28, 2021 1:33 AM 27 days ago

    Greetings Frank,

    Sorry for late response. Hopefully this can still be of some help.

    Your understanding is largely correct, as noted below:

    In normal operation, the device will have some (usually small) ripple present at both analog outputs, at twice the RF input frequency. By choosing MFLT and PFLT capacitors according to the application, the designer can customize for the best tradeoff between output ripple vs output response time (or output bandwidth). In this application, the output BW and RF input frequency are well separated, so there should be no problem with the tradeoff.

    Yes, the circle with X in the middle is the phase detector. In this implementation its a EX-OR, so that means the center of the linear phase detection range is 90 degrees. It means the two inputs should normally be configured for phase quadrature, to give widest phase detection range. The EX-OR outputs digitally, and the information is in the form of duty-cycle, so good averaging is important to achieving good accuracy.

    Filtering at the output via R6, C9 should work almost as well as adding capacitor at PFLT pin. Accuracy may be better to do the filtering at PFLT pin, provided for exactly this purpose, because this way the amplifier on chip doesn't alter the averaging function so much. Errors from the amplifier slew rate limiting are greatly reduced.  It's OK to put scope probe on PFLT pin and choose the PFLT capacitance for only a small amount of ripple on that pin.

    Also on the same subject, with regard to the page 16 formula, remember for the filter to be effective, the time constant must be somewhat longer than just one cycle of RF input (1/5e6 seconds). Solving for T= time constant = 1/(24e3) should get you close to your desired value. To be more precise, there's a factor of 2*pi. See below:

    VBW= 1/(2*pi*R*C)


    VBW = VMAG or VPHS 'video' output bandwidth, Hz.

    R= 3.3k ohms

    C= external_C + internal_C = CFLT + 1.5pF

    (in this application, the internal_C = 1.5pF can be neglected).

    Hope that answers all your questions.   -Bruce H.

  • Hello Bruce,

    This sure helps.


    On page 1 of the pdf, it says that the input impedance of INPA INPB is 3 k ohm parallel with 2 pF at low frequencies.At what frequency is is still considered low? Is it 500MHz? We use the chip between 5MHz and 30 MHz. Is that still 3k and 2pF?


    We are using the chip in a microprocessor system with ADC. We have phase output that goes nearly the full 0.0V to 1.8V span. Is there any quick correction we can apply to the AD8302 to get only the linear region of the transfer curve, or apply correction to the output to straighten the curve at the two ends?


    Well, it's not really a question, it's an observation.  This equation VBW= 1/(2*pi*R*C) with R=3k is matching more the experimental data we measured with the capacitor we use. I originally calculated a 12nF with the formula of T(ns)=3.3 * Cave. Our phase output was very attenuated. I put next 1nF and the signal bandwidth went through.



  • +1
    •  Analog Employees 
    on Jan 28, 2021 10:14 PM 26 days ago in reply to franke

    Hi Frank,

    A1) Yes, 30MHz would be considered low frequency for modeling or matching purposes.  When you get up around UHF, the inductance of the internal bond wires comes more into play, along with other parasitics which are captured in the Smith chart of Figure 6. Note that most customers do not bother with reactive matching, because while it boosts sensitivity, it degrades frequency flatness, compared to the simple case of resistive matching with the 52.3 Ohm resistors as shown on the eval board schematic. AD8302 is already quite sensitive, so usually no need to enhance it any further. 

    A2) The AD8302 phase response 'rounds' near the ends because internally the EX-OR pulses are getting narrow. The higher the RF input frequency, also the narrower, hence more rounding for higher RF frequencies. There's really nothing that can be done about it, except for perhaps an external circuit that might work as follows: You could have the microprocessor drive a transistor switch that capacitively (or inductively) shifts the phase of one input on digital command. That lets the microprocessor shift the whole phase curve left or right, away from the rounded region, and into the flat region. Of course you would need to know how much (how many degrees) the phase shifted with that digital command, so that you could compensate for the intentional offset. 

    A3) That's good news!

    -Bruce H.