ADF4372 phase adjust

Dear Kudret

Could you please provide more information as to the use of the phase adjust  function on the ADF4372. I want to send new phase values at a rapid rate ( > 100ksamples/sec) to simulate digital phase noise.

Could you please provide the sequence of register writes to do this, and answer the following questions:

1/-  Can I write to a single phase register ( 1B,1C and 1D) ?  Does the new phase adjust take place immediately?

2/- Does bit 6 of reg 1A  switch the phase adjust on and off, or does it load the new phase value?

3/- Is the new phase value double buffered, ie do I need to write to reg 10 to enable the new phase value?

4/- Can I use stream mode to write reg 1B,1C and 1D?

5/- What is the usage of bits 5:4  in reg 23 ( CLK_DIV_MODE) ?

best regards

Cosmo Little

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