Post Go back to editing

ADF4112 Fvco


I am currently reviewing the ADF4112 fVCO. We would like to study if we can simulate the FSK feature in ADF4112

Following equation is the VCO frequency:

fVCO = [(P × B) + A] fREFIN/R

Output frequency is generated by A&B counter, R divider and P prescaler.

Assume FREFIN fixed, could we can simulate FSK frequency shift feature by changing parameter?

Like intermittent programming LATCH value, such as P prescaler. I check the timing diagram and it should be feasible.

Appreciate if you have any advice.

Thank you.


  • The only standalone PLLs we have that support FSK natively with dedicated trigger pins are the ADF4158/ADF4159/ADF4169, the HMC700 and the HMC703.

    I don't have any specific reference designs for implementing FSK with ADF4112 or any of our other standalone PLLs but I don't see a reason it wouldn't be possible. I guess you are limited by how quick you can change frequency, so a wide LBW would be preferable. Also, keep SPI clock high (max is 50MHz).

    With the ADF4112, to change frequency (assuming REFIN remains same) normally all that is required is one SPI write to N register with new A/B counter values.



  • Also, ADIsimPLL can be used to design loop filter. Some of our PLL models in ADIsimPLL can also support FM modulation anaylsis. In ADIsimPLL please go to help>help topics and search for modulation for more information

Reply Children
No Data