AD8302 Impedance Analyzer 4.5-50MHz

Hey there,
I am a bit of a beginner in the electronics world, so forgive me if I ask stupid questions.
My goal is to build an impedance analyzer for the range of 4.5 - 50 MHz. To this end I am using an AD9851 DDS signal generator and an AD8302 is the core of the board.
Thus far I have managed to get it working but I still have some noise issues (especially in the phase measurement). I have included a scan from approx. 3 MHz to 50 MHz to show the response I am getting from a 16MHz HC49U-S crystal. There seems to be some general noise on both gain and phase lines. I am actually most interested in the gain measurement, but perhaps the phase measurement can give a clue as to why things are going wrong in the first place. At expected the quartz shows resonance at 16MHz and 48MHz (3rd overtone), but the 3rd overtone seems to show a lower gain (this is possible, I guess?) but more importantly also seems to show attenuation of the signal right next to the gain (resonance) part. That is something I do not really understand. I would greatly appreciate it if someone could perhaps give me a clue as to why this is happening. From my beginners understanding it is of course possible that I overlooked something somewhere else in the design, but perhaps someone has seen such a thing before? I fully understand if this is too broad of a question to answer and I would like to share my full design with you if you want, but I thought I might keep my first post relatively short.

I suspect my noise can be due to several problems. One of which is the AD8302 configuration on my PCB. I have followed the following schematic from the applications note and I am powering
the IC with +5V. I use supply coupling capacitors C7 and C6 (0.1 uF and 100 pF). For Cc I use 1 nF capacitors and R1=R2=52.3 Ohm, this should be a high pass filter with f_cutoff at 3MHz.
For the FLT capacitors I use 1 pF and I read that this is the minimum recommended value. In the datasheet (see fig 2 below) a comment is made about the bandwidth (30MHz) and that it is influenced by the value of the FLT capacitors. Am I correct in saying that higher values for the FLT caps will result in a longer signal integration time and a lower bandwidth? Could it be beneficial for my measurements to use caps with higher values?

I was also wondering if my high pass cut-off frequency was chosen correctly, as I understand that cut-offs in passive filters are no step response but are more of a sloped attenuation.

Any help, suggestions would be greatly appreciated!

Parents
  • +1
    •  Analog Employees 
    on Dec 19, 2020 3:11 AM 2 months ago

    Hi there,

    First let me say good job on this. A lot of people never get nearly as far as this, and with such good results so far.

    Be aware that AD8302 uses a very simple phase detector, an EX-OR logic function. This type of phase detector only has 180 degrees of unambiguous range. Beyond that, there will be ambiguity. AD8302 is really ideal for applications where the phase of the input signals is nominally in the range of phase-quadrature, meaning around 90 degrees typically, with 180 degrees total measurement range.

    To debug questions about the crystal behavior, it will help to zoom in much closer to look in detail. Fortunately DDS's are quite capable of that.

    The output bandwidth is around 30 MHz, each output, as-is, with low value filter capacitors or no filter capacitors. Add extra capacitance to the MFLT and PFLT pins to reduce this bandwidth to be somewhat less than the lowest RF input frequency. Too much capacitance delays the response, and too little capacitance adds output ripple and noise.  

    Since this application has a specific RF input frequency range already defined, it will be worthwhile to check the circuit capacitor values to be sure the accuracy is good across the desired range. This is most easily done with 2 signal generators, one on each input. Move both generator frequencies together across the band, maintaining a slight offset frequency. Look for flat magnitude measurement across the band, and for output bandwidth that rolls off less than the lowest RF input frequency.

    The capacitors that affect low-frequency response are the input DC blocks on pins 2 and 6, and the offset cancellation capacitors on pins 3 and 5. They are discussed in datasheet but if any questions please ask. MFLT and PFLT capacitors are relevant here also but already discussed.

    -Bruce H.

Reply
  • +1
    •  Analog Employees 
    on Dec 19, 2020 3:11 AM 2 months ago

    Hi there,

    First let me say good job on this. A lot of people never get nearly as far as this, and with such good results so far.

    Be aware that AD8302 uses a very simple phase detector, an EX-OR logic function. This type of phase detector only has 180 degrees of unambiguous range. Beyond that, there will be ambiguity. AD8302 is really ideal for applications where the phase of the input signals is nominally in the range of phase-quadrature, meaning around 90 degrees typically, with 180 degrees total measurement range.

    To debug questions about the crystal behavior, it will help to zoom in much closer to look in detail. Fortunately DDS's are quite capable of that.

    The output bandwidth is around 30 MHz, each output, as-is, with low value filter capacitors or no filter capacitors. Add extra capacitance to the MFLT and PFLT pins to reduce this bandwidth to be somewhat less than the lowest RF input frequency. Too much capacitance delays the response, and too little capacitance adds output ripple and noise.  

    Since this application has a specific RF input frequency range already defined, it will be worthwhile to check the circuit capacitor values to be sure the accuracy is good across the desired range. This is most easily done with 2 signal generators, one on each input. Move both generator frequencies together across the band, maintaining a slight offset frequency. Look for flat magnitude measurement across the band, and for output bandwidth that rolls off less than the lowest RF input frequency.

    The capacitors that affect low-frequency response are the input DC blocks on pins 2 and 6, and the offset cancellation capacitors on pins 3 and 5. They are discussed in datasheet but if any questions please ask. MFLT and PFLT capacitors are relevant here also but already discussed.

    -Bruce H.

Children
  • Hi Bruce,
    First of all, thank you for the elaborate answer! I did some more reading and found that I named my device incorrectly. I am actually designing a scalar network analyzer instead of an impedance analyzer. (I do not care much about the phase measurement yet)

    I will definitely test your suggestions. I do not understand this part of your suggestion: 'Add extra capacitance to the MFLT and PFLT pins to reduce this bandwidth to be somewhat less than the lowest RF input frequency.' What do I gain from adding capacitance to reduce the bandwidth to below my lowest RF input frequency? As you say, the response will be delayed, but does this result in a more accurate measurement?

    It might be a bit unrelated to the AD8302 and I am not sure if it is part of your expertise, but do you think that the PCB design could also play a critical part in the noise production at these frequencies?

    Have a nice Sunday!
    Cheers,
    Rens

  • 0
    •  Analog Employees 
    on Dec 22, 2020 1:17 AM 2 months ago in reply to Xerrorable

    Hi Rens,

    It's the detector output bandwidth (aka Video bandwidth) that must be less than the lowest RF input frequency. The reason is that non-coherent detection generally needs more than one cycle of RF input waveform, in order to give an accurate output. Internal to AD8302, the magnitude output before filtering resembles cycles of half-sine waveforms, like a full-wave bridge rectifier. Without filtering to average out the DC value, the AC component would override the DC average component.

    Similar explanation applies to the AD8302 phase detector, although the waveforms are different and depend on the phase relationship of the input signals.

    For AD8302, both detector video outputs have bandwidth that can be approximated as 1/ (2*pi*R*C), where R= 3.3k, and C= (CFLT + 1.5pF).

    A simple test for output filtering is to use oscilloscope on the outputs, when testing at the lowest RF input frequencies. The AC component should only be a small fraction of the DC component.

    ----------------------

    Regarding PC layout, it's probably not too critical for below 50 MHz. Nonetheless, we always recommend following the recommended layout guidelines for the IC. The power supply decoupling and ground plane should be good to 2.6GHz or higher, because the IC can have a lot of gain up to 2.6GHz and beyond. The factory eval board layout files and pictures are available for this purpose.   -Bruce H.

  • Hey Bruce,
    Thanks for taking the time to answer my questions. I did some more reading into the video bandwidth and I think it is indeed something I can play with. Today is my final day of lab work, as I am actually a chemical engineer, so tomorrow I can start playing with the electronics at home, haha. Electronics is so much fun.

    For the PCB I tried to follow the specified design as closely as possible. I just used some bigger components (0805) to make soldering easier :)

    I was actually wondering if you also know something about the AD9851, since it is also an Analog product. Right now I have a 125 MHz crystal as reference clock and I was wondering if going any higher, say 180 MHz, could be beneficial. The 30 MHz crystal with frequency multiplier did seem noisier than the 125 MHz.

    Again, many thanks for all the help and suggestions. I will keep you posted.
    I'd like to wish you a merry Christmas already.

    Cheers,
    Rens

  • 0
    •  Analog Employees 
    on Dec 23, 2020 2:07 AM 2 months ago in reply to Xerrorable

    Hi Rens,

    May I suggest you start a new Engineer Zone thread, and mention the AD9851 in the subject line? Somebody in that group should see your post and respond.

    Thanks and a merry Christmas to you and yours!   -Bruce