I am a bit of a beginner in the electronics world, so forgive me if I ask stupid questions.
My goal is to build an impedance analyzer for the range of 4.5 - 50 MHz. To this end I am using an AD9851 DDS signal generator and an AD8302 is the core of the board.
Thus far I have managed to get it working but I still have some noise issues (especially in the phase measurement). I have included a scan from approx. 3 MHz to 50 MHz to show the response I am getting from a 16MHz HC49U-S crystal. There seems to be some general noise on both gain and phase lines. I am actually most interested in the gain measurement, but perhaps the phase measurement can give a clue as to why things are going wrong in the first place. At expected the quartz shows resonance at 16MHz and 48MHz (3rd overtone), but the 3rd overtone seems to show a lower gain (this is possible, I guess?) but more importantly also seems to show attenuation of the signal right next to the gain (resonance) part. That is something I do not really understand. I would greatly appreciate it if someone could perhaps give me a clue as to why this is happening. From my beginners understanding it is of course possible that I overlooked something somewhere else in the design, but perhaps someone has seen such a thing before? I fully understand if this is too broad of a question to answer and I would like to share my full design with you if you want, but I thought I might keep my first post relatively short.
I suspect my noise can be due to several problems. One of which is the AD8302 configuration on my PCB. I have followed the following schematic from the applications note and I am powering
the IC with +5V. I use supply coupling capacitors C7 and C6 (0.1 uF and 100 pF). For Cc I use 1 nF capacitors and R1=R2=52.3 Ohm, this should be a high pass filter with f_cutoff at 3MHz.
For the FLT capacitors I use 1 pF and I read that this is the minimum recommended value. In the datasheet (see fig 2 below) a comment is made about the bandwidth (30MHz) and that it is influenced by the value of the FLT capacitors. Am I correct in saying that higher values for the FLT caps will result in a longer signal integration time and a lower bandwidth? Could it be beneficial for my measurements to use caps with higher values?
I was also wondering if my high pass cut-off frequency was chosen correctly, as I understand that cut-offs in passive filters are no step response but are more of a sloped attenuation.
Any help, suggestions would be greatly appreciated!