I'm a DFAE in Japan. The customer evaluates EV-ADF4159EB and has two questions as follows.
Q1. In the Ramp waveform shown below, there is only one place where the voltage level is lower than the other. I marked it in yellow. On the other hand, this phenomenon does not occur in sawtooth mode. Please tell me how to improve this.
Q2. Is there a way to shorten the time shown in blue, preferably zero? The customer saies that time is the time to launch LE. I think it can be adjusted with the TIMER setting. What do you think?
Can you send screenshots of their register writes with the software GUI (main controls and ramps and shift keying tab). Are they using default VCO and loop filter?
Thank you very much for your quick response. What is meaning software GUI? ADI SimPLL?
You mentioned they are using ADF4159 eval board, so I assumed they are using ADI's ADF4158 software GUI. If so, could you send two screenshots of the software when they have configured the board so I can see how they are programming the device. (see below example of GUI). If their are using their own software to control the board then their list of register writes is fine.
ADIsimPLL file would also be useful if they are not using the default VCO/loop filter. If the customer is using the board's default loop filter it may not be optimized for their particular ramp configuration. Please see this video for more information
With their register writes and details on their loop filter/VCO I can advise what could be improved on their design
The customer thinks the frequency chirping and hopping. For example, chirp 5.5GHz <=> 5.6GHz, hop 5.6GHz to 5.7GHz and chirp 5.7GHz <=> 5.8GHz by triangular mode. However, he is beginning to find it difficult to achieve with the ADF4159. Could you please advise if there is any good way. You can use another IC instead of ADF4159. How about HMC701?