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About ADF4372

Hello,

     I have some trouble in test of ADF4372. The output signal is show in figure,and could not be changed through SPI .But form the sdo , we can see that  the data has been shifted into the register successfully.

     And the output power could be changed lower through SPI. But the output frequency has not change after the data has been shifted into REG 0x1A to 0X10.

    Besides ,when 0x4c is writen to 0x20, the muxout output  low logic level . and when 0x5c is writen to 0x20, the muxout output high logic level . And the muxout could output high logic level of 3.3V in the setting of high.   What can I do to debug this PLL?

Thank you!

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