Hi everyone, I have some questions about the design of loop filter as shown in the page 9 of the HMC3716 datasheet:
- What's the output of NU & ND? The phase error between RF and LO is represented by the voltage on NU and ND? For example, if there is a fixed phase error between RF and LO(with same frequence), what might be the voltage on NU and ND? And the 2Vpp swing of NU ND is due to the voltage drop accorss 200 ohm resistor ? 10mA * 200 = 2V .
The output at ND/NU is a 2V swing from 3V to 5V with the internal 200Ohm pull up resistors. These are narrow voltage pulses which will get more narrow at the devices locks.
ADIsimPLL is free software of…
ADIsimPLL is free software of ours and it has the HMC3716 model which can be used to design your loop filter. There are a few instructional videos on ADisimPLL if you require here on EZ.
Please see here and also here for more information. If you require further assistance after reading these please let me know.
Hi, aandrews! Thanks for answering.I've read the material you provided. I have some follow up questions.
- How to understand the hysteresis associated with the output phase error and amplitude? Where does the hysteresis come form?
- How to understand the voltage pulse at NU/ND? Can i take it as a PWM wave, with low level bring 3V and high level being 5V. The phase error between 0 and 2pi is represented by the length of 3V/5V. And the mean value of voltage pulse therefore vary between 3V~5V. So, from my understanding, phase error being a constant like pi will contribute to a voltage of 4V at NU?ND. Am i right?
Many thanks and regards! Hope for your reply soon.
These PFDs were designed to be used closed loop in a complete synthesizer application so by mentioning the hysteresis it is to try and make users know that there could be issues when using these devices as a simple phase detector as they weren't designed/tested/characterised for this. We do not have much data on it other than this
I think this helps explain your second question. The output will be closer to 5V when lock is declared.