I'm working on a design using an ADAR1000 and ADTR1107. We need to switch between transmit and receive states every ~10ms or so. We plan to use the ADAR's TR pin to switch between transmit and receive states. Reading the documentation, I noticed that the ADAR takes care of the bias control for the LNA and PA, switching to the proper ON and OFF voltage levels when you switch to TX and RX.
However, the ADTR1107 datasheet describes the proper power sequencing when switching to TX and to RX states, and it involves setting VDD_PA to 0V in RX state, and VDD_LNA to 0V in TX state.
I wonder how to properly switch modes in this situation, as keeping VDD_PA and VDD_LNA at all time on would violate the recommended power sequence, and the LNA would remain self-biased unless I set the bias control to pinch it off while in TX state. It will also waste a lot of power.
Also, implementing load switches to dynamically turn VDD_PA and VDD_LNA on and off where needed would create a chicken and egg problem with the bias control. If VDD_PA is turned on before the TR pin swiched to TX state, VDD_PA be on in RX state for a brief moment. If VDD_PA is turned on after the TR pin switches to TX state, then the bias controller will set VGG_PA to the "on" bias level before VDD_PA is present, violating the turn on sequence. This will require fast load switches or voltage regulators.
I'm probably missing something here but I can't see what it is. Could you please clarify how to properly power things up in this situation? We want to minimize the control line and power rails required for the board, as there's a serious area constraint.
EDIT: I forgot about the PA_ON pin, which seems to solve the issue for TX state. Set TR pin to TX, power-on VDD_PA, set PA_ON to set the bias to the proper level. Still not sure how to proceed with the LNA for RX state.
You can switch between tx and Rx there is no concern about violation. The sequence outline is assuming you are evaluating one side at a time. not very realistic in a full fledged system. I…
The switch, LNA and ADAR1000 can share the same +3.3V supply.
The ADAR1000 can apply ON and OFF voltages to each PA gate (4 PA_BIAS pins) and all the LNA gates (1 LNA_BIAS pin). These pins and their voltages…
The switch only has to be powered up once. It doesn't have to be power down when changing between Tx and Rx. It is important to apply the switch bias voltages in the proper sequence. VDD_SW , VSS_SW, then CTRL_SW.
Yes, we plan to power VDD_SW and VSS_SW from fixed power supplies. In fact, VDD_SW is always powered, with its 3.3V rail shared with ADAR100's AVDD3. VSS_SW is post-regulated to -3.3V from ADAR's AVDD1.
My concern is with ADTR1107's VDD_LNA and VDD_PA, and how to turn them on and off while switching from transmit to receive state, without violating the sequences from page 24 of the datasheet.
You can switch between tx and Rx there is no concern about violation. The sequence outline is assuming you are evaluating one side at a time. not very realistic in a full fledged system. I apologize for that.
To switch the PA off just Put VGG to -2V, switch to Rx. Power on the LNA.
Also you can leave the PA and LNA fully biased and just switch the switch between Tx & Rx. Powering down the side not in use depends on whether you have a power consumption concern and want to save power.
It really doesn't matter which amp is powered up first. The important thing is when powering up the switch VDD_SW is applied first.
Ok, thank you very much for the answer, it's clear now.
If I understand it correctly, this means that VDD_LNA (3.3V) could be shared with ADAR1000's AVDD3 and also VDD_SW, having all three power inputs connected to the same voltage rail, as there's no sequencing required for VDD_LNA. Do you foresee any potential issue with that? I would connect the power good line from this rail's regulator to the enable pin of the voltage inverter supplying the negative rails, to ensure VSS_SW sequencing compliance.
Joining all the 3.3V power pins in the same rail would simplify the board layout a lot, which is already quite cramped and there aren't too many layers available for power distribution.
Then, I could leave both amplifier's VDD on at all times, turning the amplifiers on and off by playing with the VGG bias levels, which the ADAR1000 automatically does, right?
Also, would there be any issue if I also power VDD_PA at 3.3V and tie it to the same voltage rail also supplying VDD_LNA, ADAR1000's AVDD3 and VDD_SW? We can live with the lower OP1dB and Psat.
The ADAR1000 can apply ON and OFF voltages to each PA gate (4 PA_BIAS pins) and all the LNA gates (1 LNA_BIAS pin). These pins and their voltages follow the Tx and Rx mode of the ADAR1000.
The PA cannot really share the same +3.3V supply rail due to sequencing issues. The ADAR1000 powers up with the BIAS_CTRL bit set to low (register 0x30, Bit). This makes the PA_BIASx pins to use the EXT_PAx_BIAS_ON registers to set the voltage bias, and by default this is 0V. (see table 18 in the ADAR1000 Rev. A datasheet) Having 0V on the PA gate while the VDD_PA is powered up would cause damage to the PA. You must setup the PA_BIASx voltages first, before turning on the VDD_PA supply rail.
Okay, so, combining both answers from Jim and you:
VDD_LNA can be turned on at any time, as it's self-biasing thus it won't destroy itself.
The PA isn't self-biased, so VDD_PA has to be turned on with VGG_PA sufficiently negative to fully turn it off, or at least sufficiently negative so that it doesn't let too much current in I.e. VDD_PA has to be turned on with VGG_PA sufficiently negative to set the bias current wtithin spec, less negative than that (for example 0V) and the PA fries itself, right?
So two voltage rails it is. One for ADAR, LNA and switch, and other for PA. Turn ADAR on, configure properly, ensure proper config and then turn on PA, and play with the VGG_PA bias level to turn the PA on and off as needed, which is automatically done by the ADAR1000 if properly configured.
I think it's all clear now, thank you very much.