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ADF4371 with HMC1031/ADF4002, 20dB Phase Noise hit at 100Hz Foffset


I have an eval for the ADF4371 and I'm using an HMC1031 eval to lock the 100MHz ref to a precision 10MHz OCXO.  I am generating an 18GHz LO.  As seen here:

The problem here is measured PN at 100Hz offset.  With the on-board crystal reference PN @ 100Hz = -87dBc/Hz.  With HMC1031 PN @ 100Hz = -67dBc/Hz.

Notable design parameters:

- HMC1031 Loop BW set to 10Hz as outlined in the spec sheet page 12.

- 100MHz VCXO, CVHD-950, CMOS output

- The measure slew rate from the HMC1031/CVHD-950 better than on board 100MHz reference.

Thanks in advance!


Added other parts to title
[edited by: aandrews at 4:14 PM (GMT -4) on 24 Sep 2021]
  • Hi Chris,

    The Flicker FOM of HMC1031 is -252dBc/Hz. This gives -112dBc/Hz @ 100Hz offset @ 100MHz output.
    PNFLICK = Flicker FOM + 20log(fVCXO) − 10log(fOFFSET)

    If this is transferred to 18GHz;
    -112 -20log(18G/100M) = -67dBc/Hz.

    If I did not make any mistake in calculations, math says that your measurement is very accurate. The contributions from other sources (OCXO, VCXO, PLL floor FOM, loop filter) are not significant.

    When using CVHD in open loop, I would also expect to see something close to -87dBc/Hz. But it is possible that the instrument cannot track the signal as you advised. Perhaps you can try to force Vtune to a mid-level instead of connecting it to GND. Min and max levels might be problematic.


  • Hi Kazim,

    So based on the recommendations here:

    It looks like the ADF4002 would be a good fit to improve my phase noise performance by an additional 7dB based on the improved 1/f FOM of -259dBc/Hz of the ADF4002 vs. -252dBc/Hz for the HMC1031.

    However, I am not able to realize the performance suggested by the ADF4002 model in ADIsimPLL.  I am seeing generally the same performance with both the ADF4002 and the HMC1031.  I've been through a couple iterations on the loop filter and have double checked the setting in the Integer N software.  So I'm kind of stuck, any suggestions?



Reply Children
  • Hi Chris,

    Is it possible that you are around the measurement limits of your signal source analyzer? 


  • Hi Kudret,

    For the ADF4002 or the HMC1031 at 100MHz yes.  But at 18GHz output from the ADF4371 is definitely in the measurement range.  Switching between the 4002 and the 1031 as reference for the ADF4371 PN performance is degraded using the 4002 at all offsets.



  • Hi Chris,

    HMC1031 is dominating element for the 100Hz PN.

    When using ADF4002, it is possible that OCXO, VCXO and other elements are also contributing. CVHD-950 datasheet typical spec is -119dBc/Hz at 100Hz offset for 100MHz output. Can you please check the PN of OCXO? Did you model these components in ADIsimPLL when simulating your circuit?

    At these low levels supply noise may also affect the measurements.How do you power the ADF4002 and CVHD-950, are you using LDOs? Can you check with different bench power supplies? Is it possible to share the screenshot of your measurements?

    Regards, Kazim

  • Hi Kazim,

    I do not have an instrument that can measure PN of an OCXO.  So I rely on the measurements at RF to imply the PN at the reference frequency.

    I did model the 4002 in ADIsimPLL I can share if you would like to see it.  The SW shows -118dBc/Hz at 100Hz offset.  This would imply -72dBc/Hz at 18GHz.  This is acceptable if I could realize it.

    I am powering the ADF4002 eval unit from bench supplies.  I will try some other supplies and see if there is any improvements seen.  I will also share some screenshots of the measurements soon.



  • Hi Kazim,

    As seen below I was able to realize some improvement in PN performance of the ADF4002 by reducing power supply noise.  PN measured at 18GHz.

    PN plot:

    However, by implementing similar changes to the 1031 circuit I was able to improve the performance of that as well and it still outperforms the 4002.

  • Hi Chris,

    Using the battery as the supply is the best. Good to see that worked fine. It looks like the loop bandwidth of two setups are highly different.

    In HMC1031 measurement, the slope is 20dB/decade which is probably the PN of on-board VCXO. Then I would guess the LBW is very narrow, around 10Hz. Also I cannot see any filter corner for first loop, just a corner for ADF4371.

    On the other hand, the 10dB/decade slope indicates the 1/f noise of the ADF4002 and there is a corner around 5kHz which supposed to be the LBW. What is the simulated LBW in ADIsimPLL for ADF4002? What is the VCO gain that you used for simulation?

    Regards, Kazim

  • Hi Chris,

    Could you also please send your 4 writes to ADF4002 for the first setup too?



  • Hi Kazim,

    Yes, you are correct the LBW for the 1031 is set to 10Hz and the 4002 is 5kHz.  I initially tried to design a 10Hz loop filter for the 4002 but it was looking like the values were unrealizable or unusually large at least.  So I set LBW to 5kHz thinking the 100Hz offset was going to be dominated by the chip anyway and I could revisit the LBW after I confirmed the performance.  I will take another look at this.

    Here is the tuning gain used for the SimPLL model, data points are measured:

  • Hi Alex,

    I did not write any code to program the 4002 yet so I'm not sure how the data is being written.  I am using the SW provided with the eval kit at the moment.

    Here are the settings and reg values: