ADAR1000 Beam Switching Start Address

Hello,

I have a question related to the ADAR1000 beam stepping mechanism using RAM.

In the related section of the datasheet it is mentioned that the registers 0x04D - 0x050 should hold the TX & RX start & stop address.

But what exactly should I put there?

Is it the TX beam ram position index (so 0 - 121)?

Or should it be the actual address of the RAM register, but in this case from which channel? This address by the way would be 16 Bits - so should I write just the lower 8 Bits?

I tried both, filling in the RAM index, as well as the lower 8 Bits of the RAM address of index 0 from channel 1, but did not get useful results

- which altough could be related to other problems in the configuration.

My configuration is, in order to achieve that the bias voltages are taken from SPI Regs but the beam positions are taken from RAM:

  • REG_MISC_ENABLES (0x030) = 0x5F
  • REG_MEM_CTRL (0x038) = 0x2C
  • REG_SW_CTRL (0x031) = 0x04

I additionally configure the TX baem positions 0 - 2 in RAM to 0°, 45° , 90°.

The external PA bias voltages and the LNA bias voltage switch on/off by toggling the TR pin, which works fine. Just the beam switching using RAM does not create the expected phase shifts.

I use the ADAR1000-Evalz connected to a microcontroller through connector P1 - SPI interface, TR pin, TX_LOAD pin, RX_LOAD pin and PA_ON pin pulled HIGH for testing.

Does anybody have a clue what could be wrong here?

Thanks!

  • 0
    •  Analog Employees 
    on Sep 4, 2020 2:20 PM 2 months ago

    You should write the beam position index to registers 0x4D to 0x50.  Are you applying 6 or more clock cycles to load the RAM data and doing the steps outlined below?

    1. Write the desired 7-bit starting beam position to Reg 0x04D (TX) or 0x04F (RX)
    2. Write the desired 7-bit stopping beam position to Reg 0x04E (TX) or 0x050 (RX)
    3. Apply ≥6 SCLK cycles to load in the starting beam position from memory
    4. Pulse the TXLOAD or RXLOAD pin for the starting beam position to take effect
    5. Apply ≥6 SCLK cycles to load in the next beam position from memory
    6. Pulse the TXLOAD or RXLOAD pin for the next beam position to take effect
    7. Repeat steps 5 and 6 to sequentially step through the beam positions stored in memory. After the stopping beam position has been loaded, the sequence will return to the starting beam position and repeat.
  • Hello!

    Thanks for your fast reply, unfortunately I was topped up with other projects with tight deadlines and could not return on this one before now.

    I tried again to run the ADAR chip from RAM and followed the above mentioned steps. It kind of works, thank you.

    BUT some of the configured phase switches are unprecise. e.g. when I try to shift it 45° I get 48° instead.

    AND I get a consistent problem:

    My test setup consists of 3 TX Beam Positions stored in RAM on positions 0 = 0°, 1 = 45°, 2 = 90°. The starting beam position is set to index 0, the stopping beam position is set to index 2.

    I start by switching the TR pin to LOW to simulate receiving mode, then I switch the TR pin to HIGH to enter transmitting mode and start pulsing the Serial Clock line and subsequently the TXLOAD pin with the following results:

    • After the first switch squence (should be on index 0) I get the phase shift for position 1 instead of the shift of position 0. Which should be 45° but really is 48° as mentioned above.
    • Then on the next switch sequence (should be on index 1) the phase shift does not change at all.
    • Then on the next switch sequence (should be on index 2) I get to 90° as expected.
    • Then on the next switch sequence (should be on index 0) I finally get my expected 0° phase shift.
    • Then on the next switch sequence (should be on index 1) I get 48° phase shift.
    • Then on the next switch sequence (should be on index 0) I get 90° again.

    Then I start all over again by switching to RX mode and then back to TX mode and the whole thing starts again.

    Is this a known problem that after switching from RX mode to TX mode the RAM is somehow messed up?

    Do you have ever experienced something like that and/or know how to solve this issue?

    I verified that the RAM position 0 for TX is configured correctly after getting the wrong phase shift and it always is...

    Is there a way to verify the current RAM index that the internal counter is pointing to?

    Any help is appreciated, thanks in advance!

    Best Regards,

    EDIT:

    In order to get the ADAR chip to work I have been playing around with some configurations and so I did not realize that I keep getting the above mentioned behaviour only if I try to turn off and on the beam stepping option right after switching from receive mode to transmit mode (with the TR pin).

    Removing this "hack" caused a change in behaviour - it is still not working as described in the datasheet but it gets closer. I used the same test setup as mentioned above, I wrote to 3 positions in RAM the phase shifts: 0°, 45°, 90° in this order.

    The result after switching from RX mode to TX Mode and applying the 6 clock pulses on SCL + one on TXLOAD was as above, at first. I still keep getting the phase shift from position 1 - instead of position zero.

    But afterwards I get the phase shift from position 0, followed by the phase switch of position 1, then 2, then it restarts at 1, ... and so on. Until the next RX/TX mode switch. Then the cycle repeats.

    Hopefully this extra information helps you understanding what's going on.

    Best Regards,

  • 0
    •  Analog Employees 
    on Sep 24, 2020 2:28 PM 2 months ago in reply to Stonebull

    Can you post exactly what you're writing to the SPI, and with some pseudo-code for the other digital operations with the TR, TX_LOAD, and RX_LOAD, and the exact sequence of everything?  Please put the SPI values with Address Value, then Data Value.  So for example:

    Addr         Data

    0x0038    0x2C    //Bias Ram bypass & enable Tx & Rx beam step

    0x1800    0xFF   //Set position 0, Ch 1, Tx VGA

    0x1801    0x36   //Set postion 0, Ch 1, Tx I vector

    0x1802    0x35  //set position 0, Ch 1, Tx Q vector

    -> set TR pin to high-

    > Provide 6 sck cycles

    -> Strobe TX_LOAD pin

    I don't think I can debug this any more without knowing exactly what you're doing with the device.

  • Hello!

    Thanks for taking your time, again apologises for my late response.

    I wrote my whole init sequence and the subsequent beam switching routine as pseudo code below:

    ADAR1000 Initialization Sequence for Beam Stepping from RAM
    
    R/W	Addr		Data
    
    W	0x000		0xBD	//Reset whole chip, use SDO line for readback, address auto incrementing in block write mode.
    
    W	0x00A		0xAA	//Write to scratch pad for testing SPI connection
    R 	0x00A		-		//Read from scratch pad
    
    W	0x401		0x10	//Allow LDO adjustments from user settings.
    W	0x400		0x55	//Adjust LDOs.
    
    W	0x046 - 49	0x60	//Setup external PA Bias OFF levels for RX mode for each channel to approximately −1.8 V in receive mode.
    
    W	0x029 - 2C	0x28	//Setup external PA Bias ON level for TX mode for each channel to approximately −0.8 V in transmit mode.
    
    W	0x034 		0x08	//Setup RX internal LNA Bias to 8
    W	0x035		0x16	//Set receive VGA bias to 2, vector modulator bias to 6.
    W	0x02D		0x28 	//Set external LNA_BIAS to approximately −0.8 V.
    
    
    W 	0x030 		0x5F 	//Enable LNA_BIAS (LNA_BIAS_OUT_EN), select output to follow TX/RX Mode (BIAS_CTRL). Enable Power Detectors for all channels
    W 	0x038 		0x2C 	//Select SPI Regs instead of internal RAM for Bias channel settings, but use RAM for Beam channel settings, Turn on TX & RX Beam Step enable
    
    W 	0x031		0xC2	//Select TR input for transmit and receive switching control, disables TX_EN & RX_EN
    
    W	0x036		0x16	//Setup TX internal Bias - Set transmit VGA bias to 2, vector modulator bias to 6.
    W	0x037		0x06	//Set transmit driver bias to 6.
    
    //Setup TX attenuator, Gain & Beam Position for each Channel
    //Set Channel 1-4 attenuator to 0 dB, VGA gain to maximum.
    W 	0x01C - 1F 	0xFF	
    W	0x020 - 27	0xFF
    
    //Setup RX attenuator, Gain & Beam Position for each Channel
    //Set Channel 1-4 attenuator to 0 dB, VGA gain to maximum.
    W 	0x010 - 13 	0xFF	
    W	0x014 - 1B	0xFF
    
    W	0x02E		0x7F	//Select all four receive channel, enable receive LNA, vector modulator and VGA.
    W 	0x02F		0x7F	/Select all four transmit channel and enable transmit driver, vector modulator, and VGA.
    
    //Set-up RAM
    //---------------------------------------------------------------------------------------------------------------
    
    //RX BEAM
    //---------------------------------------------------------------------------------------------------------------
    
    //RX BEAM - POS 0 - CH 1 to 45°
    W 	0x1000		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1001		0x36	//Set receiver I vector and polarity values for Channel 2;
    W	0x1002		0x35	//Set receiver Q vector and polarity values for Channel 2;
    
    //RX BEAM - POS 0 - CH 2 to 45°
    W 	0x1004		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1005		0x36	//Set receiver I vector and polarity values for Channel 2;
    W	0x1006		0x35	//Set receiver Q vector and polarity values for Channel 2;
    
    //RX BEAM - POS 0 - CH 3 to 45°
    W 	0x1008		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1009		0x36	//Set receiver I vector and polarity values for Channel 2;
    W	0x100A		0x35	//Set receiver Q vector and polarity values for Channel 2;
    
    //RX BEAM - POS 0 - CH 4 to 45°
    W 	0x100C		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x100D		0x36	//Set receiver I vector and polarity values for Channel 2;
    W	0x100E		0x35	//Set receiver Q vector and polarity values for Channel 2;
    
    //TX BEAM
    //---------------------------------------------------------------------------------------------------------------
    
    //Pos 0 => 0°
    //---------------------------------------------------------------------------------------------------------------
    
    //TX BEAM - POS 0 - CH 1 to 0°
    W 	0x1800		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1801		0x3F	//Set receiver I vector and polarity values for Channel 2;
    W	0x1802		0x20	//Set receiver Q vector and polarity values for Channel 2;
    
    //TX BEAM - POS 0 - CH 2 to 0°
    W 	0x1804		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1805		0x3F	//Set receiver I vector and polarity values for Channel 2;
    W	0x1806		0x20	//Set receiver Q vector and polarity values for Channel 2;
    
    //TX BEAM - POS 0 - CH 3 to 0°
    W 	0x1808		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1809		0x3F	//Set receiver I vector and polarity values for Channel 2;
    W	0x180A		0x20	//Set receiver Q vector and polarity values for Channel 2;
    
    //TX BEAM - POS 0 - CH 4 to 0°
    W 	0x180C		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x180D		0x3F	//Set receiver I vector and polarity values for Channel 2;
    W	0x180E		0x20	//Set receiver Q vector and polarity values for Channel 2;
    
    //Pos 1 => 45°
    //---------------------------------------------------------------------------------------------------------------
    
    //TX BEAM - POS 1 - CH 1 to 45°
    W 	0x1810		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1811		0x36	//Set receiver I vector and polarity values for Channel 2;
    W	0x1812		0x35	//Set receiver Q vector and polarity values for Channel 2;
    
    //TX BEAM - POS 1 - CH 2 to 45°
    W 	0x1814		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1815		0x36	//Set receiver I vector and polarity values for Channel 2;
    W	0x1816		0x35	//Set receiver Q vector and polarity values for Channel 2;
    
    //TX BEAM - POS 1 - CH 3 to 45°
    W 	0x1818		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1819		0x36	//Set receiver I vector and polarity values for Channel 2;
    W	0x181A		0x35	//Set receiver Q vector and polarity values for Channel 2;
    
    //TX BEAM - POS 1 - CH 4 to 45°
    W 	0x181C		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x181D		0x36	//Set receiver I vector and polarity values for Channel 2;
    W	0x181E		0x35	//Set receiver Q vector and polarity values for Channel 2;
    
    
    //Pos 2 => 90°
    //---------------------------------------------------------------------------------------------------------------
    
    //TX BEAM - POS 2 - CH 1 to 90°
    W 	0x1820		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1821		0x21	//Set receiver I vector and polarity values for Channel 2;
    W	0x1822		0x3D	//Set receiver Q vector and polarity values for Channel 2;
    		
    //TX BEAM - POS 2 - CH 2 to 90°
    W 	0x1824		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1825		0x21	//Set receiver I vector and polarity values for Channel 2;
    W	0x1826		0x3D	//Set receiver Q vector and polarity values for Channel 2;
    		
    //TX BEAM - POS 2 - CH 3 to 90°
    W 	0x1828		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x1829		0x21	//Set receiver I vector and polarity values for Channel 2;
    W	0x182A		0x3D	//Set receiver Q vector and polarity values for Channel 2;
    		
    //TX BEAM - POS 2 - CH 4 to 90°
    W 	0x182C		0xFF	//Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB
    W	0x182D		0x21	//Set receiver I vector and polarity values for Channel 2;
    W	0x182E		0x3D	//Set receiver Q vector and polarity values for Channel 2;
    
    
    //Setup RAM stepping Control
    //---------------------------------------------------------------------------------------------------------------
    W	0x04F		0x00	//Set up the start RAM Position for beam stepping for RX channels
    W	0x050		0x00	//Set up the stop RAM Position for beam stepping for RX channels
    W	0x04D		0x00	//Set up the start RAM Position for beam stepping for TX channels
    W	0x04E		0x02	//Set up the stop RAM Position for beam stepping for TX channels
    
    //-------------------------------------END OF INIT SEQUENCE -------------------------------------------------------
    
    //Beam switching Test:
    while(1)
    {
    	//1° round
    	//---------------------------------------------------------------------------------------------------------------
    	
    	//Write min 6x Clocks & 1 pulse to TX_LOAD -> expected index 0 = 0°
    	//---------------------------------------------------------------------------------------------------------------	
    	W	0x00A		0xAA	//Write something to scratch pad to generate at least 6 pulses on SPI serial clock line
    	
    	Write '1' to TX_LOAD pin
    	Write '0' to TX_LOAD pin to simulate a pulse
    	
    	=> Set phase difference marker of network analyzer to 0°
    	
    	//Write min 6x Clocks & 1 pulse to TX_LOAD -> expected index 1 = 45°
    	//---------------------------------------------------------------------------------------------------------------	
    	W	0x00A		0xAA	//Write something to scratch pad to generate at least 6 pulses on SPI serial clock line
    	
    	Write '1' to TX_LOAD pin
    	Write '0' to TX_LOAD pin to simulate a pulse
    	
    	=> Phase difference marker of network analyzer remains on 0°
    
    	//Write min 6x Clocks & 1 pulse to TX_LOAD -> expected index 2 = 90°
    	//---------------------------------------------------------------------------------------------------------------
    	W	0x00A		0xAA	//Write something to scratch pad to generate at least 6 pulses on SPI serial clock line
    	
    	Write '1' to TX_LOAD pin
    	Write '0' to TX_LOAD pin to simulate a pulse
    	
    	=> Phase difference marker of network analyzer jumps to 45°
    	
    	//2° round
    	//---------------------------------------------------------------------------------------------------------------
    	
    	/Write min 6x Clocks & 1 pulse to TX_LOAD -> expected index 0 = 0°
    	//---------------------------------------------------------------------------------------------------------------
    	W	0x00A		0xAA	//Write something to scratch pad to generate at least 6 pulses on SPI serial clock line
    	
    	Write '1' to TX_LOAD pin
    	Write '0' to TX_LOAD pin to simulate a pulse
    	
    	=> Phase difference marker of network analyzer jumps to -45°
    	
    	/Write min 6x Clocks & 1 pulse to TX_LOAD -> expected index 1 = 45°
    	//---------------------------------------------------------------------------------------------------------------
    	W	0x00A		0xAA	//Write something to scratch pad to generate at least 6 pulses on SPI serial clock line
    	
    	Write '1' to TX_LOAD pin
    	Write '0' to TX_LOAD pin to simulate a pulse
    	
    	=> Phase difference marker of network analyzer jumps to -0°
    	
    	/Write min 6x Clocks & 1 pulse to TX_LOAD -> expected index 2 = 90°
    	//---------------------------------------------------------------------------------------------------------------
    	W	0x00A		0xAA	//Write something to scratch pad to generate at least 6 pulses on SPI serial clock line
    	
    	Write '1' to TX_LOAD pin
    	Write '0' to TX_LOAD pin to simulate a pulse
    	
    	=> Phase difference marker of network analyzer jumps to 45°
    	=> The phase shift is always off by 1 position
    }
    
    
    
    
    
    

    I hope you can understand what I am doing and be able to understand if it's a configuration problem and how I can solve it.

    If anything is unclear don't hesitate to ask me, I'll try to be more fast at responding this time.

    Another question arose during cuircuit developement for the ADAR1000.

    Can you tell me how much power the receive port (RX1-4) of the ADAR chip can withstand whilest the device operates in transmit mode?

    Thanks for your time,

    Best Regards,

  • Hello,

    I was wondering if you could find the time to look through the pseudo code example that I sent to you in my last post.

    I do not mean to push you by any means (considering myself have not been too fast at replying in the past either) but the deadline is coming closer and the ADAR chip stepping mechanism is a crucial part of the current project, which is still buggy...

    Best Regards,