Did you measure it on the evalboard or did you produce your own board? Could you please share the snapshot of your top layer including vias if its your own PCB?
Could you please tell the EN state and CTL state? Please make sure they are not floated initially. Also I wonder if you see the same values for different EN states.
It would make sense to increase the power output of the network analyzer and reducing the IF bandwidth for better isolation. I see that you have already achieved 61dB. Achieving higher isolation depends on your measurement environment as well.
I can measure 70dB around 1.5GHz. It would make sense to use further shielding and absorber if you have any.
What is the solder paste thickness you use also?
Increasing the power and reducing IF BW unfortunately didn’t make any impact on the isolation. 61 dB is achieved for EN is 0 (SW is disabled). Otherwise for EN = 0 (SW is enabled), we continue to have 40 dB isolation.
By the way, do you measure the isolation with a shielding or absorber on your demoboard? Can the reason be your 4-layer eval-board instead of our 2-layer PCB?