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ADRF5721 and ADRF5731 compatibility of SEROUT pin with SPI Bus connected to multiple devices

I want to use this on an SPI bus with other parts.

Is the SEROUT line tri-stated OPEN when LE=High, and only driven when LE=LOW?

In other words, do I need to put a tri-state buffer or switch between the SEROUT pin and the MOSI pin on the bus master?

This info needs to be added to the data sheet.

  • Hi JWM, 

    With the ADRF5721/31 properly biased, the SEROUT on the attenuator is always GND or VDD. Out device doesn’t have a high Z mode.
    Depending on your application, you may need to add a tri-state buffer.

    We will look into the suggested datasheet changes.


  • HK,


    That means it is vital that you get ADI to correct the fallacious data sheet!

    Delete the text stating it "supports a 3-wire SPI" - It does not! SPI requires a tri-state output!!

    If you say anything about SPI, you need to add a figure showing HOW to make a circuit that IS SPI compatible.

    i.e. with a tri-state buffer or switch that creates a tri-state output based on LE.

    And  revise Figure 22 to show the clock gated with LE, or change the text, which ever is correct.

    Why is ADI dragging on this? Why is this not being done or done already? Can you get ADI to pay for the board re-spin caused by this fallacious "supports a 3-wire SPI"  statement please?

  • Hi JWM, 

    We have already updated the datasheet for ADRF5720.

    The datasheets for the remaining products (ADRF5730/21/31) are being currently under revision and are going through the internal approval process at the moment. These should be completed shortly.


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