ADRF5721 and ADRF5731 compatibility of SEROUT pin with SPI Bus connected to multiple devices

I want to use this on an SPI bus with other parts.

Is the SEROUT line tri-stated OPEN when LE=High, and only driven when LE=LOW?

In other words, do I need to put a tri-state buffer or switch between the SEROUT pin and the MOSI pin on the bus master?

This info needs to be added to the data sheet.

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  • The only answer I got was that it is probably not SPI compatible on its own. You need to add your own tri-state buffer.

    I'm not sure why this answer has not been confirmed here by now.

    The engineer I talked with said he would recommend up the chain that they:

    (1) revise Figure 22 to show the clock gated with LE, and either

    (2) delete the text stating it "supports a 3-wire SPI", and show a diagram of how to make it compatible with SPI--i.e. with a tri-state buffer or switch, or

    (3) add to Figure 22 a tri-state buffer prior to the output, that is controlled by LE.

Reply
  • The only answer I got was that it is probably not SPI compatible on its own. You need to add your own tri-state buffer.

    I'm not sure why this answer has not been confirmed here by now.

    The engineer I talked with said he would recommend up the chain that they:

    (1) revise Figure 22 to show the clock gated with LE, and either

    (2) delete the text stating it "supports a 3-wire SPI", and show a diagram of how to make it compatible with SPI--i.e. with a tri-state buffer or switch, or

    (3) add to Figure 22 a tri-state buffer prior to the output, that is controlled by LE.

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