HMC4069:Output signal loss lock under some given frequency

Hi! I have some problems when using HMC4069 together with LT6200 and an external VCO(Crystek), i have an input signal of 40MHz. I set the N divider 2., and want to get signal of double frequency. I made the design using ADISimPLL, The bandwidth of LPF is 60KHz, phase margin is 70°. But it only performs normally in a region of frequency(from 45MHz to 37MHz), when the input signal frequency is below 37MHz,it is unlocked. But when the input frequency drops to 34MHz, it  locks again, which troubles me a lot. Any ideas or solutions on this issue? Can it be the design of LPF that causing this problem? Thanks a lot for help:)

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