I have the following questions regarding the datasheet for ADPA7005CHIP (Rev. 0):
1.) In table 3 (Absolute Maximum Ratings) the maximum gate voltage VGG1 is specified as -1.5V to 0V.
The bias sequence of the “Applications Information” stated to set the gate voltages VGG1 and VGG2 to -2V.
Can you please tell me the recommended gate voltage VGG1 / VGG2 for the biasing sequence?
2.) In table 7 (Power Selection Table) the different currents for I_DQ with the resulting gains and power consumption are specified.
In table 3 (Absolute Maximum Ratings) the maximum power consumption P_Diss is specified as 13.4W.
Conversely, does this mean that a current flow of I_DQ = 2.68A and consequently an even higher gain would be possible?
3.) Must the bias sequence always be performed or would it theoretically be sufficient to perform it once to determine the gate voltage at which a current of I_DQ = 1.2A is flowing?
I would like to integrate the biasing chip HMC980LP4E, but here it is only available from December 2020. Of course I can also solve the bias sequence with a separate circuit, but this would cost me effort and space.
Best regards,
Sonja
