I am using the ADRF6821 with a REF in of 10 MHz and set it's up with internal VCO. The intended freq at the LO-out pin should be 900 MHz. This is according the datasheet the minimum that's possible. This set-up was working on the evaluation board + GUI software of analog devices. Now i am using it with my own firmware, by programming via SPI all the low level registers. What i have observed sofar is that:
The 2xLO freq is too low e.g. 718 MHz and it's not locked since it does drift over time.
Even when i enable the 2xLO with NO 10 MHz REF in connected i still get the 718 MHz on the 2xLO pin.
Is the sequence in with the low level registers are programmed critical?
What is the prefferred low level registers programming sequence?
I hope that some can provide me a good idea to solve this issue. Thanks Leo
Great News Leo !
I'm glad it worked. Let me know if you have further questions.
It's probably best to first download the register settings from the ADI evaluation board, and compare to the registers in your internal board.
Hi Darrell, Thank you for your reply.
When i posted my question i realized that my description was not complete. Indeed what you propose was one of the 1st things i did including capturing all the SPI signals with a digitizer on the evalution board, since that was considered as my reference. On the evaluation board i found that if all the required settings in the GUI are done and at the end you click the apply changes + Pll adjust button the signal appear as they should be.
So indeed these setting are send on my firmware board to the ADRF6821 chip.
Maybe i should ask, when or what can cause that there is no signal the 2xLO-out pin, it seems like some kind of free running signal that is there. (As stated not the intended 900 MHz) even when i change the integer setting the freq, does not change.
--> Correction Red arrow should be at LO Out (not at EXT LO in)
It's good to hear the ADI EVB worked for you. It sounds like the internal LO loop isn't locked on the new board. Let's verify you have a 50 ohm resistor to gnd at the REF In port, pin , and that the level is +10 dBm. You can also try different REF frequencies, such as 10 Mhz with /1, or 40 Mhz with /4, etc.
I'm not familiar with any requirements on programming sequence but will explore that further.
Let me know if the REF levels look ok and then we'll try other steps.
Hi Darell, Thanks for all your good ideas.
Last days i structually checked the complete firmware code and the register settings.
Guess what: I found a register setting that was wrong and that seems to be crucial......
I made a typo in the BLOCK_RESETS (0x10,0x21), when i filled it with (0xFF) the correct freq does appear on the 2xLO out pin and the PLL is now locked as well.
Conclucion: Problem found and solved.