ADF4371 with 5 MHz passive loop bandwidth filter


I need to design a loop bandwidth filter for the ADF4371 with 5 MHz BW, but I want to avoid using op-amps since they increase the noise and jitter. Is this feasible? can someone share a topology that works? I am stuck in ADISimPLL between error 608 and 503 and can't seem to find a working design despite trying different values of Icp and sweeping the phase... I just need a 5 MHz bandwidth so my PLL can track periodic jitter of up to that much.

Thank you,