In the Supply Current section of the specification, there are two low power sleep modes: hardware power down and software power down. Is this correct with the following recognition?
In both cases, the register settings are retaind unless the supply voltage is removed.
If the register value is held, can we consider the time from the sleep state to the lock state to be only the PLL lock-up time shown in data sheet figure31?
Our application requires intermittent transmission and reception, and low power consumption, so we want to sleep PLL while transceiver is waiting.
The current consumption is 500uA for hardware power down, 1000uA for software power down, I would like to chose the latter, but is there a disadvantage?
Could you tell us the difference in IC status between the two power-down modes?
Hi,Yes, your configuration is correct for power down modes.The difference is; the register contents are lost in hardware power down. In software power down, the register contents are retained. In this…
Hi,Yes, your configuration is correct for power down modes.The difference is; the register contents are lost in hardware power down. In software power down, the register contents are retained. In this regard, software power down is more suitable to your application. I do not see any disadvantage. The time from sleep to lock state will also include biasing the internal blocks, buffers, etc. But I expect the main contributor still be the autocalibration so same lock time can be considered. Note that register 0 must be written after software power-up to initialize the autocalibration. Faster lock time is possible by bypassing the autocalibration as explained in AN-1353, but that requires some extra register writing.www.analog.com/.../AN-1353.pdfRegards,