ADAR1000 questions


All document references below refer to the ADAR1000 datasheet (Rev. A) and to

I) Questions related to beam stepping
In our application we will need the system to operate in one of several operating
modes. Each such mode is associated with a set of beam positions. Stepping between
beam positions will be performed via the TX_LOAD, RX_LOAD interface.
Note: we will never load the working registers directly. That is, we will write beam
data to memory locations (starting from address 0x1000) and effect them by pulsing
Beam position memory will be logically divided into two sets - positions 1-60 and
positions 61-120.
While the system operates in a given mode, the ADAR1000 will be repetitively cycled
between the positions belonging to one of the sets (may need to perform any number
of such cycles before switching to another mode). While operating in a mode, our
firmware will load the beam positions belonging to the other set (via SPI) to allow
quick mode switching when required.
Note: the above beam cycling while operating in a given mode will be performed by
only pulsing TX_LOAD and RX_LOAD (will provide at least 6 SPI clock cycles between
successive TX_LOAD or RX_LOAD pulses). This relies on the ADAR1000 automatically
reception of the next TX/RX_LOAD pulse (according to the datasheet errata document it
does behave that way).
A request to switch modes arrives to our system from outside (asynchronously to beam
generation). Our system acts upon such request after completing the last beam in the
current set.
A very important issue for us is making mode switching as fast as possible to
minimize the time during which the system is unusable.
We plan on implementing mode switching by our firmware writing to SPI registers
0x04D-0x050 (assuming of course that beam position memory belonging to the new mode
has already been set up) and then pulsing TX_LOAD and RX_LOAD (to load the beam data
of the first beam in the new set).
We plan on using the fastest possible SPI clock (25 MHz).
I have the following questions:
1. Upon reception of a TX_LOAD pulse how does the ADAR1000 know whether to load the
   next sequential TX beam position or the position specified in register 0x04D?
   Is the action of SPI writing to register 0x04D (or 0x04E) serves to reset its
   internal state machine with respect to how it processes TX_LOAD pulses?
2. Is it necessary to maintain a particular phase relationship between SPI clock and
   TX_LOAD or RX_LOAD? Or is it only necessary to provide (at least) 6 SPI clocks
   between successive pulses on TX_LOAD or RX_LOAD?
   I am asking this question because in Figure 69 TX_LOAD seems to be asserted
   synchronous to SPI clock negation.
3. Regarding Figure 70:
   a) Why is there a transition from transmit position 1 to transmit
      position 2 following a pulse on the TR input (rather than on the TX_LOAD
   b) It is my understanding that pulsing TX_LOAD causes ADAR1000 (assuming that it
      is configured to use memory data as opposed to SPI data) to internally load
      TX parameters from the next TX beam position memory location. This data will
      be actually used when the device is (or is switched to) TX state. Ditto RX. Am
      I correct?
4. In the answers provide in
   it is indicated that when using TX_LOAD and RX_LOAD to step between beams it is
   best to avoid any SPI activity (other than generating the proper amount of SPI
   clock pulses).
   This is very problematic for us since, as explained above, we need to pulse
   TX_LOAD and RX_LOAD all the time and in addition need to access registers via SPI
   (for loading beam position memory, for writing to registers 0x04D-0x50 and also
   for other unrelated needs, e.g. power detector monitoring).
   What are the limitations on using SPI in conjunction with beam stepping?
II) Additional questions (unrelated to beam stepping)
1. Figure 15 - what is the meaning of phase shift of hundreds of degrees? Ditto
   Figure 34.
2. Specific register programming-related questions:
   2.1) Register 0x000:
        a) From the example on p. 39 I presume that reset is self-clearing.
        b) Is there a need to perform a delay between issuing soft reset request by
           writing to register 0 with bits 0 and 7 set and issuing the next command
           (any command) to the device?
           Note: we are planning to use the maximum possible SPI clock rate
           (25 MHz).
   2.2) Register 0x032:
        a) What is the polarity of the ADC_CLKFREQ_SEL bit? Does 1 in this bit
           selects the 2 MHz or 250 KHz ADC clock frequency?
        b) Is there any advantage to selecting 250 KHz clock frequency (e.g. higher
           reading accuracy, etc.)?
   2.3) Registers 0x035, 0x036:
        SPI programming example sets receive and transmit VGA bias to 2, receive and
        transmit VM bias to 6.

        These values are not listed in Table 6 (they are neither the nominal values
        nor the low-power values). Assuming that we want to use highest-performance
        mode, should we use the values provided in Table 6 or the values in the SPI
        programming example?
        This is important since we need all the RF performance that we can get (linearity,
        noise figure, gain, etc.).
   2.4) Registers 0x400, 0x401 - why would an application want to perform LDO

        The SPI programming example includes programming for these registers. The
        datasheet errata document does describe these registers, however it doesn't
        say what it is good for.
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