All document references below refer to the ADAR1000 datasheet (Rev. A) and to
Please see my answers below in bold.
1. Upon reception of a TX_LOAD pulse how does the ADAR1000 know whether to load the next sequential TX beam position or the position specified in register 0x04D? Is the action of SPI writing to register 0x04D (or 0x04E) serves to reset its internal state machine with respect to how it processes TX_LOAD pulses? [A] It probably won't know that you have a new BEAM_STEP_START value without de-asserting the TX_BEAM_STEP_EN (Or RX_BEAM_STEP_EN) bit in Reg 0x38. This should reinitialize sequencer state machine with any new memory start/stop values. 2. Is it necessary to maintain a particular phase relationship between SPI clock and TX_LOAD or RX_LOAD? Or is it only necessary to provide (at least) 6 SPI clocks between successive pulses on TX_LOAD or RX_LOAD? I am asking this question because in Figure 69 TX_LOAD seems to be asserted synchronous to SPI clock negation. [A] TX_LOAD & RX_LOAD should be asynchronous relative to the clock, although there could be a hold-time requirement between the 6th clock cycle and rising edge of TX/RX_LOAD. This should be really small. If you want to be safe, allow for an additional 1/2 clock cycle before strobing TX/RX_LOAD (as shown in Figure 69). I think the reason TX/RX_LOAD is synchronous to the clock in Figure 69 is because both signals are being driven from the same pattern generator. 3. Regarding Figure 70: a) Why is there a transition from transmit position 1 to transmit position 2 following a pulse on the TR input (rather than on the TX_LOAD input)? [A] This might be a typo; RX_LOAD and TX_LOAD could have been tied together. Let me inquire about this. b) It is my understanding that pulsing TX_LOAD causes ADAR1000 (assuming that it is configured to use memory data as opposed to SPI data) to internally load TX parameters from the next TX beam position memory location. This data will be actually used when the device is (or is switched to) TX state. Ditto RX. Am I correct? [A] Correct. 4. In the answers provide in ez.analog.com/.../347241 it is indicated that when using TX_LOAD and RX_LOAD to step between beams it is best to avoid any SPI activity (other than generating the proper amount of SPI clock pulses). This is very problematic for us since, as explained above, we need to pulse TX_LOAD and RX_LOAD all the time and in addition need to access registers via SPI (for loading beam position memory, for writing to registers 0x04D-0x50 and also for other unrelated needs, e.g. power detector monitoring). What are the limitations on using SPI in conjunction with beam stepping? [A] You can probably use the regular SPI writes to provide the 6+ clock cycles. I don't know what will happen exactly, if you are in the middle of a SPI, for example clocking in bit 10 of 24 bits, and you strobe the RX/TX_LOAD. 1. Figure 15 - what is the meaning of phase shift of hundreds of degrees? Ditto Figure 34. [A] It is the phase shift, or phase variation, over temperature. What is shown is what is phase measured by a VNA. 0 degrees phase setting doesn't yield 0 degrees on the VNA. This is because the VNA is measuring phase between its 2 ports. But the difference in phase of phase_setting_0deg - phase_setting_45deg, should be 45 degrees. The graph then shows how this varies over temperature. 2. Specific register programming-related questions: 2.1) Register 0x000: a) From the example on p. 39 I presume that reset is self-clearing. [A] The reset bits are self clearing. I would seperate the reset SPI Write, with the other SPI writes to Reg 0x00. It seems that the reset command overwrites any other data in Reg 0x00 if done in the same SPI write. b) Is there a need to perform a delay between issuing soft reset request by writing to register 0 with bits 0 and 7 set and issuing the next command (any command) to the device? Note: we are planning to use the maximum possible SPI clock rate (25 MHz). [A] Standard setup and hold times should be sufficient for a reset to take effect. 2.2) Register 0x032: a) What is the polarity of the ADC_CLKFREQ_SEL bit? Does 1 in this bit selects the 2 MHz or 250 KHz ADC clock frequency? [A] Low should use the 2MHz clock High should use the 250kHz clock b) Is there any advantage to selecting 250 KHz clock frequency (e.g. higher reading accuracy, etc.)? [A] I don't think so, but I can check. 2.3) Registers 0x035, 0x036: SPI programming example sets receive and transmit VGA bias to 2, receive and transmit VM bias to 6. These values are not listed in Table 6 (they are neither the nominal values nor the low-power values). Assuming that we want to use highest-performance mode, should we use the values provided in Table 6 or the values in the SPI programming example? This is important since we need all the RF performance that we can get (linearity, noise figure, gain, etc.). [A] Please use nominal bias for best overall RF performance. Those are out-dated bias numbers. 2.4) Registers 0x400, 0x401 - why would an application want to perform LDO trimming? The SPI programming example includes programming for these registers. The datasheet errata document does describe these registers, however it doesn't say what it is good for. [A] Early on in development there was concern for LDO variation over process. The LDOs are pretty close to nominal values without trimming. Not trimming should not affect anything.
Thank you very much for your answers. I would like to clarify a few issues (mainly related to beam stepping and SPI communication), as follows:
1. You wrote: " I don't know what will happen exactly, if you are in the middle of a SPI, for example clocking in bit 10 of 24 bits, and you strobe the RX/TX_LOAD. "
This issue is critical for us - as I described in my original post we need to jump quickly between two sets of beam positions. For that we need to update beam position data of some beam positions in memory while the ADAR1000 is using other positions (via beam stepping).
a) Perhaps if need to combine beam stepping with SPI communication, TX_LOAD and RX_LOAD should be pulsed at particular bit positions of the SPI communication? Or are you saying that TX_LOAD and RX_LOAD should only be pulsed while the chip select is deasserted?
b) If indeed TX/RX_LOAD must only be pulsed while chip select is deasserted - are there any timing requirements on the relationship between chip select deassertion and the leading edge of TX/RX_LOAD?
c) We need to pulse TX_LOAD and RX_LOAD at very precise times (these lines will be controlled by an FPGA). If have to avoid pulsing these lines in the middle of SPI communication, will will abort any ongoing SPI transaction when need to pulse these lines.
c1) Can an SPI transaction (read or write) be aborted in the middle (by deasserting chip select) at any point in time (asynchronously to SPI clock)?
c2) What is the minimal delay between aborting such communication (deassertion of chip select) and the leading edge ot TX/RX_LOAD?
Again, these issue are critical to our application.
2.Figure 70 in the datasheet shows RX_LOAD pulsed somewhat after TR transition from RX to TX.
Note: we plan on using the TR line (rather than SPI) for transitioning between RX and TX, so the above figure applies to our case.
a) I presume that a leading edge of TX_LOAD should occur while TR is low and a leading edge of RX_LOAD should occur while TR is high. Am I correct?
b) What are the timing constraints on the relative timing between the leading edge of TX_LOAD, RX_LOAD and TR transitions?
c) What is the minimal required pulse width on TX_LOAD, RX_LOAD?
3. You wrote: It probably won't know that you have a new BEAM_STEP_START value without de-asserting the TX_BEAM_STEP_EN (Or RX_BEAM_STEP_EN) bit in Reg 0x38. This should reinitialize sequencer state machine with any new memory start/stop values."
I planned on setting the above bits during initialization and never touching them after that.
a) Am I to understand that when we need to jump between the two sets of beam positions, in addition to updating registers 0x4D through 0x50 we also need to pulse (->0->1) the above bits in register 0x38?
b) Can I rely on the beamformer ignoring the update to registers 0x04D through 0x050 until I write to register 0x038 and that in particular if I pulse TX_LOAD/RX_LOAD between the update to registers 0x04D through 0x050 and the write(s) to register 0x038, the beamformer will continue using the old TX/RX_BEAM_STEP_START and _STOP values?
This is important for us since the total time to update registers 0x04D through 0x050 and additionally write twice to register 0x038 is significant in our case. Thus I would like to start the update earlier than the start of the last beam, if possible.
4. Regarding the setting of registers 0x035, 0x036 you wrote: "Please use nominal bias for best overall RF performance. Those are out-dated bias numbers."
So to achieve best RF performance should we use the values in Table 6 or the values used in the SPI programming example ?
Thank you very much for your assistance.
Continuing my previous post regarding the issue of performing beam stepping via TX/RX_LOAD in parallel with SPI communication:
1. I would like to point out that while performing beam stepping we need not write to memory locations that are between TX/RX_BEAM_STEP_START and TX/RX_BEAM_STEP_STOP - we do need to write memory locations that are outside that range (and subsequently modify the START and STOP registers to point at the new range).
Additionally, we need to monitor power detector inputs in the background.
Given the above, is it still a problem to pulse TX/RX_LOAD in the middle of SPI transactions?
2. If the answer to the previous question is yes, i.e. we must terminate an ongoing SPI transactions in the middle (by deasserting chip select) in order to be able to pulse TX/RX_LOAD - it is obviously possible to terminate such transaction on a byte boundary (when doing for block write transfer). I have the following questions:
a) Can an SPI transaction be safely terminated while transferring 16-bit address word? Between the address word and the following (first or only) data byte?
b) What is the minimum delay between chip select deassertion and the leading edge of TX/RX_LOAD?
Thank you very much for your assistance. We really need it.