I'm trying to build PLL synthesizer based on ADF4169 PLL and HMC735 VCO. It's assumed to cover a bandwidth of 1 GHz with center frequency at 11.18 GHz. I've designed the loop filter for this application with LBW 100 kHz using ADIsimPLL. The reference is 10 MHz sine wave TXCO with output power about -2 dBm. The EVAL-ADF4159 Evaluation Board works with this reference correct.
At first, I've tried to implement the loop filter using OP184 op amp. So, the PLL could lock the desired frequency and assert LD only with Rdoubler disabled and Neg Bleed current disabled. But the phase noise performance seems to be very poor, it contains also the row of spurs at kHz-offsets, which have significant level (pic 1). If I try to implement Rdoubler and Neg Bleed current, the PLL can't lock the desired frequency at all.
Then I've tried to change the op amp and use the AD8510. Now if I don't implement Rdoubler and Neg Bleed current, this picture does not change. If I implement these features, the PLL produces desired frequency, the phase noise performance seems to be much better (pic 2), but the ADF4169 does not assert the LD signal.
And so are my questions:
1. If I use an op amp with wider GBP (I mean AD8065, for example), could I expect that LD operation will be more robust?
2. The LOL and LDP bits in R3 register are set to 1 (according to the datasheet, to more robust operation). May it be useful to change these bits?
3. Maybe I have not taken into account another significant issues, but they all seem to be correct. The power supplies are clear, the PCB is not multilayer and is manufactured on appropriate microwave material, all signal tracks are 50 Ohms matched.
Thank you in advance.