I am using the ADF5901+ADF4159 chip combination to generate an FMCW ramp from 24GHz to 24.25GHz. However, the voltage on the VTUNE pin is always zero. I've been debugging the chips to figure out the problem. I have some questions in this context.
1. With the Vtune voltage at 0, will there be a spike in the current consumption in the ADF5901 chip, when the PUP Tx1 and PUP LO bits in register 0 are set to 1? If there is no spike in the current consumption, is it safe to assume that the VCO chip is broken?
2. How do we decide the BW and phase margin for the loop filter? My PFD frequency is 40MHz (REFIn:40M) and the required FMCW bandwidth is around 240MHz. I am using a loop filter designed earlier by my colleague. I am not familiar with loop filters. I've entered the filter components in the ADIsimPLL software and noticed that the BW and phase margin was 340KHz and 350deg respectively. Is this design correct?
3. If there is no feedback signal coming from the VCO (AUX and ~AUX), can the PLL still generate the ramp voltage if all the registers are set properly?
t oget a good basic knowledge of PLL / VCO please read the article at the following page .
For use of the ADIsimPLL see the following
then read the ADF5901 datasheet and the ADF4159 datasheet from our web page.
following on from that ...please order ( if you havent one already ) the EV-ADF5901SD2Z ( with the SDP controller board) to understand the operation of both components,
re the questions above ..
1. Could be due to a number of reasons, an understanding of the above is necessary
2.BW of 340khz is ok but the phase margin should be closer to 45degs
3.no, feedback from the ADF5901 to the ADF4159 is required.