I am looking to get the footprint of this amplifier layout as small as possible. I have a few questions regarding the layout of the evaluation circuit shown on Figure 40, page 13 of the datasheet.
1. Are the trace lengths and widths from the device pins to any one of the bypass capacitors (assuming I’m using the same dielectric constant substrate for my layout) important to keep to?
2. Are the trace lengths and widths for the VDD and VGG bias lines important to keep to?
3. If possible, I would like to move most of the bypass capacitors like C5 and C6 as close to the pins as possible and will be stacking another PCB on top of this one to bias it. Will this be okay?
4. What part # / voltage rating do you recommend for C2, C3?
5. What part # do you recommend for C5?
1) Trace widths on the RFIN &RFOUT line are important as the must be designed for a 50 ohm characteristic impedance.
2) The traces for VDD lines need to be wide enough to support the current that is flowing through them to the DUT. VGG current consumption is low so width isn't critical. Ideally you would like to keep the lengths as short as possible.
3) yes, bypass capacitors should be place as close as possible to the pins.
4) C2 7 C3 have 100 V rating. C2: TDK, C2012X7S2A105K, C3 TDK, CGA2B3X7s2A103K050BB
5) C5&C6: KEMET, C0603C101F1GACTU, 100V.
Gerber files maybe downloaded from https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-HMC8205.html#eb-overview