Our customer is evaluate the EV-ADF5610SD1Z, and check the SPI timing.
Following is the captures signals, SCK, SDI, SDO, SEN with logic analyzer.
After power - on, the SCK has 3 periods, 3~4 pulses each.
Is this pulse for selecting the open mode ?
Or what is this CLK control ?
Why does the 3 SCK periods input ?
In the datasheet 35 page,
SERIAL PORT MODE DECISION AFTER POWER-ON RESETOn power-up, both legacy mode and open mode are active and listening.
All digital inputs and outputs must be low at power-up.Selection of the desired serial port mode (protocol) is determined on the first occurrence of SEN or SCK, after which the serial port mode is fixed and only changeable by a power-down.
If a rising edge on SEN is detected first, legacy mode is selected.
If a rising edge on SCK is detected first, open mode is selected.
Unless I'm interpreting the plot you attached incorrectly it appears that all SPI lines are being held high at start up. They should be held low at start up and then depending on which mode of operation is desired (OPEN would typically be the choice) bring SCK up prior to SEN. If Legacy or HMC mode is desired then SEN would be brought up prior to SCK. The eval board does include isolators on the SPI lines which should prevent noise problems.
Perhaps there is noise still coupling onto the SPI lines causing these SCK pulses or perhaps the GUI is sending them, not sure.
It's also important to follow the power up sequence of the eval board in order to power it up in the correct mode. Refer to the User Guide for more information but the basic process is as follows.
1) Eval board powered off.
2) SDP board mounted to board and connected to PC,
3) Open GUI and 'Connect' to SDP.
4) Unplug cable from SDP board.
5) Power on EV-ADF5610SD1Z.
6) Plug cable back into SDP board.
7) Write all registers.
Let me know if you continue to have problems. Attached SPI mode app note.