I have HMC586LC4B (VCO), HMC434 (Freq Divider by 8), and HMC439QS16G (PFD). I want to build FMCW chirp 4.5 - 5.5Ghz and I have generated chirp 562.5 - 687.5 MHz as reference. But I have no idea about designing the Loop Filter to bridge my PFD and VCO.
Do you have any papers or references that I can delve into?
Thanks a lot
There's an FAQ for the HMC Phase Frequency Detectors on EZ that covers this (search EZ or look under 'Discussions' on the product page on analog.com. Additionally ADISimPLL includes the proper active loop configuration when you select the HMC439. Unless you've alreay designed in the HMC439 I'd recommend using the HMC3716 as it has slightly better ESD & noise as well as INV & LD functionality.
Thank you very much. Will check it soon.