Phase synchronization of several fractional PLL (ADF5610 & ADF4155)


We are working on a multi-channel receiver projet. Due to the routing complexitiy, two options are currently possible :

- each receiver has its own OL generation embedded (two OL based on ADF5610 and ADF4155+HMC390, boths PLL in fractional mode), a common clock reference is driving the all the synthesizers.

- or : A common synthesizer is used for everyone, the two OL signals are splited in N ways to drive the receiver mixers.

The second solution is quite hard in terms of routing because there are two RF signals (at frequencies >3GHz) to route from the divider to the mixers.

The first solution is the simplest in terms of routing : only a ref clock is needed.

We don't care about static phase differences between the ways : a calibration mechanism allows to compensate for them. And the second solution is therefore correct for us regarding the phase synchronization of the differrents ways. But our question is, in the case of N Pll synthesizers sharing the same clock reference: what about the phase difference which can appear in the system after some time running or a channel change ? How the fractional PLL mechanisms as Dithering, CSR, Pulse bleed.. etc can affect the phase and make a difference between one synthesizer and its neighbour ?

Thank you for your help.