Phase synchronization of several fractional PLL (ADF5610 & ADF4155)


We are working on a multi-channel receiver projet. Due to the routing complexitiy, two options are currently possible :

- each receiver has its own OL generation embedded (two OL based on ADF5610 and ADF4155+HMC390, boths PLL in fractional mode), a common clock reference is driving the all the synthesizers.

- or : A common synthesizer is used for everyone, the two OL signals are splited in N ways to drive the receiver mixers.

The second solution is quite hard in terms of routing because there are two RF signals (at frequencies >3GHz) to route from the divider to the mixers.

The first solution is the simplest in terms of routing : only a ref clock is needed.

We don't care about static phase differences between the ways : a calibration mechanism allows to compensate for them. And the second solution is therefore correct for us regarding the phase synchronization of the differrents ways. But our question is, in the case of N Pll synthesizers sharing the same clock reference: what about the phase difference which can appear in the system after some time running or a channel change ? How the fractional PLL mechanisms as Dithering, CSR, Pulse bleed.. etc can affect the phase and make a difference between one synthesizer and its neighbour ?

Thank you for your help.

  • +1
    •  Analog Employees 
    on Feb 4, 2020 3:07 PM over 1 year ago


    I apologize in advance for the lengthy response but hopefully it will be helpful. Before I address your concerns you should be aware that the ADF5610 has very limited phase control. Register 0x06[1:0] of the ADF5610 are 'Seed_Select' bits where the user can select one of four options: 0, LSB, or one of two  fixed "busy binary numbers". The caveat is that REG 0x06[8] = 1 (which it does since we're programming REG 0x06[10:8] = 7). The ADF4155 on the other hand, offers 23 bits for the seed value for the phase accumulator. If both are used then the ADF4155 will be the one that would primarily need to be adjusted to correct any phase imbalance downstream.  

    You are correct in that the fractional PLL functions that offer improved spurious and settling time will affect the phase. Any difference in frequency error due to fractional resolution will also of course complicate things. The ADF5610 does have the ability to eliminate the frequency error (exact frequency mode) but this may increase spurs; the ADF4155 achieves near zero hertz error with its auxiliary modulus / frac bits. Additional phase variation will exist due to layout as you mention but even if the electrical length / phase is well managed in layout, the permittivity of the PCB material and physical parameters such as the Cu will vary with temperature. Differences in localized heating or the rate of phase change over temperature of each synthesizer can induce additional differences in phase. With 2 different PLL / VCO combinations (and different methods of eliminating frequency error for instance) comes additional variation as each VCO has it's own phase drift characteristic as do the PLL phase detectors, SDM's, dividers, etc. These will each drift in phase differently over temperature. If I understand your inquiry correctly it sounds like you have some means of accounting for these differences. 

    I would recommend using the same PLL / VCO or integrated synthesizer if possible (one with phase adjust capability) for each path to minimize the number of variables and perhaps gain some economy of scale. Also do your best to achieve similar electrical lengths of the downstream path to the mixer to minimize the phase error and the rate at which the phase must be adjusted to compensate for drift over temperature. Be sure to pay attention to other discrete components in each path and within the loop filter, particularly how their value may change with voltage and temperature introducing additional phase error. 

    Best Regards,