I have designed a board with a PLL with ADF 4159. The system is designed with ADISimPLL.
The designed loop filter has a bandwidth of 650kHz and phase margin of 54deg. I have attached the design of the loop filter as screenshot. The reference frequency is 100MHz. I am using a active filter with the Op Amp LTC6228. The VCO is ROS-3600-419+.
The measured phase noise is much higher than calculation of the simulation . For the measured phase noise and the simulated phase noise see the pictures below.
I already using and changed to very low noise power supplies.This didn't changed anything. Also I have measured the phase noise of the VCO and putted this to the simulation.
a) What could be the reason for this much higher noise? In particular at the frequencies 1kHz to 100kHz from carrier?
b) I also forced the ADF 4159 to do charge pump up and down (R4 ramp status) and measured directly behind the output of the ADF 4159 before the Loop filter with a 50ohm resistor. The measured results can be seen in the picutre. For charge pump up I expect a constant voltage, or? Are the observed signals here correct?