Post Go back to editing

HMC769 probleme with charge pump output


we make a board with the HMC769 with the same schematic to the hittite board but we have a problem with the HMC769. We think that the HMC769 can communicate with the 121726-2 interface but we have 5v at the output of the charge pump even if we change the frequency of the vco (but the vco stay at 9.47Ghz since the Vtune is same). But when we force up the charge pump, we have 0.9V at the output and the vco go to 8.2Ghz... But when we force down, the charge pump do nothing and stay at 0.9V and the vco stay at 8.2Ghz.

We are new with this vco pll and we don't have a good experience. Do you have a test procedure to understand the problem ?

We are also new in the spi communication...

Thank you to help me.

good day.

Best regards.


  • It is good for me, it is the clock. There is a problem with it.

  • Looks like EZ had a problem here. 

    Anyway, glad you got it going. Let me know if you run into any other issues. 

    Best Regards, 


  • Here is a general process for troubleshooting guide for a PLL that doesn't lock. In most cases it should allow one to quickly and methodically discover the problem. 

    ►Has this device previously functioned and locked properly?   

         * Note that the answer doesn’t necessarily change the process but may prioritize it differently.

    ►Does part lock but LD not reporting properly? (verify lock with Spectrum Analyzer or SSA)?

    ►Verify register settings (review datasheet, work through equations for setting charge pump current, lock detect window, etc.). Often I find that customers experiencing lock problems with a given PLL haven't taken the time to read the datasheet and understand exactly what is required to properly program it. This is where obtaining an evaluation board 

    ►Verify test setup is correct and proper bias voltage is present at the various supply pins. 

    ►Verify that a valid reference & PFD frequency are being used for the mode of operation (SE / DIFF, INT / FRAC) is being used.

    ►Is RF output power at the expected level?   (Typically within ±1-2 dBm of expected)

         *If “No” perform board level inspection / analysis.

    ►Do register settings appear to be correct?    

         *If “No” set to default or known good conditions and re-test. Review register contents of a successfully programmed eval board. 

    ►If on board TCXO is being used, is it biased?  

    ►Using an RF probe or high impedance scope probe verify that REF output is arriving at REF input of PLL.

         *Is the REF level roughly what would be expected?     

         *Typically will measure lower than actual as it’s highly dependent on the quality and proximity of ground at the probe.

    ►If using a scope, is the REF waveform present and waveform and levels as expected (do they meet the PLL requirements for slew rate, drive?). If signal is differential are output phases complimentary?

    ►Alternatively, if using an external reference, is it enabled and is the output power correct.

    ►Is the divided down VCO signal arriving at the RF input of the PLL and is it at the proper drive level?

    ►Verify that similar DC voltages exist at both Vtune and CP and that they are not at the rail.

          *Most PLL's have a charge pump register feature that will allow the user to force the CP to the high rail or low rail. User     can view the signal on a spectrum analyzer and should be able to see the signal shifting up / down in frequency as the CP  is forced to the voltage rails. 

    ►Perform a board level visual inspection of components to verify that components aren’t damaged and are properly soldered in place, traces are intact, solder joints are acceptable, remove flux / solder balls and allow to adequately dry after cleaning. Don't forget to look at the connectors and jumpers. 

        *Eliminate tombstones, verify resistor values with DVM (depending on configuration may need to lift one side), check caps

      with DVM to verify no shorts.

        *Focus on the reference and loop filter paths first.

        *If nothing found, verify ground vias for shunt components are o.k.

        *Simulate loop filter using ADISimPLL and verify that phase margin is between 40° - 70° and that

         loop BW is reasonable. Verify closed loop response on signal analyzer is stable and similar to ADISimPLL prediction. 

        *Have seen high value capacitors not rated for +125°C can short during assembly / reflow.

    Finally,  depending on the PLL product many signals such as the REF, N counter, LD, etc. ) can be verified at the GPO pin if it exists which may simplify the process. If problems persist however, the waveform level and shape should still be verified at the input pin as often the signal is a bit distorted at the GPO pin. 

    Best Regards,


  • Hi Marty, thank you very much for your advice.  Nevertheless, there is a problem with the usb-spi interface 121726-2. Can you give me the schematic please Marty ? I think I do a mistake and the digital isolator IL717-3 is very hot. I think there is a problem. can you help me please.

    Thank you.

    Best regard.


  • Hello Mr Richardson.

    Thank you. It is good for me.

    An other question for you. My wish is to control my hmc769 with a small electronic board like arduino without a laptop.

    Do you have an advise for a electronic card (like arduino or other small electronic card)?

    Do you have any arduino or other code to control your hmc769 with a small board by spi please ?  thank you very much.

    Best regard.