I have a design based on the HMC699 PLL and HMC584 VCO with a CW output of 13.6GHz. Everything works just fine and the phase noise measurements match the simulation very good. However I have several high spurs close to the F0. The ref oscillator is 100MHZ and the pfd is 100MHz. The RFOUT/4 is input to the FIN on the PLL with a DC-block capacitor. Hence N=34 with A=3 and S=2. Anybody experienced a similar problem?
Sorry to hear your having problems with the implementation of the HMC699 + HMC584. Operating in integer mode implies that there should only be reference spurs.
There's a lot of info I don't have regarding this application (whether or not you are working with evaluation boards, exactly where the spurs are falling). A schematic / layout wasn't provided nor how the spurs change with frequency, reference, drive level, etc. so here's my thoughts based on what I have to go on.
While this may not be part of the problem I thought I should mention that the HMC699 requires a VCO drive level of -10 dBm minimum per the datasheet. The HMC534 RFOUT /4 outputs a nominal -5.5 dBm at 3.4 GHz. Depending on the path length, number and value of components in the path, when we consider process variation the drive level at the input to the HMC699 may be marginal, especially over temperature.
Note that you are operating at a Non-continuous divide ratio but this shouldn't be a problem.
As far as spurs, If good low noise, high PSRR LDO's are not being used or good RF practices for biasing are not being followed (double shielded cables, clean supplies, no fly wires) noise or RF may be coupling onto the board through the supplies or their connections resulting in the spurs you see. If all of the aforementioned items are being adhered to then perhaps environmental RF signals are the issue. You might try placing the board in a Faraday cage to eliminate any external signals and see if the spurs are reduced or eliminated.
In order to get an understanding of the origin of the spurs you'll want to determine the aggressor if you can. Evaluate how the spur location and / or magnitude change as you vary the RF frequency (does if follow A counter or S counter values, any trends?). How does it change with reference frequency. Try driving the RFOUT / 2 port, does this make a difference (much higher drive level).
Finally, this model requires the use of a particular active loop filter topology for use with the PFD of the HMC699. The series resistors should remain at 200 ohms as shown in the applications circuit in the datasheet to maintain the proper voltage swing.
Thank you for your reply,
The most dominant spurs are at 60kHz, 120kHz, 180kHz, 240kHz. I had a problem finding an explanation for that.
This is a printed circuit board with SMD components. When I did the design it seemed to be a safe idea to use the RF/4 (prescaler) output from the VCO as Ref-in for the PLL. More testing showed that this is marginal. The spurs start to grow when the temperature on the top of the HMC699 package is about 35C. It means that it takes about one minute before we see the spurs. A heatsink solved the problem.
On a testboard with only the synthesizer we don't see this problem. So it is marginal.
Thanks Leif for confirming what the problem was.
Please let me know if any additional assistance is needed.
I would like to follow up on this. We have the possibility to control the power to the syntesizer with a microcontroller. We do not need to run the synthsizer continously. I tried this and was suprised that the synthseizer needed about 65ms to start up. I expected that to take about 10us. Any ide what can cause this?