I have a design based on the HMC699 PLL and HMC584 VCO with a CW output of 13.6GHz. Everything works just fine and the phase noise measurements match the simulation very good. However I have several high spurs close to the F0. The ref oscillator is 100MHZ and the pfd is 100MHz. The RFOUT/4 is input to the FIN on the PLL with a DC-block capacitor. Hence N=34 with A=3 and S=2. Anybody experienced a similar problem?