I have several questions about designing a circuit for AD8302 working in frequency range of 20 Hz to 50 MHz.
I highly appreciated to read your opinions.
1. according to AN-691 app note, for output ripple reducing we can put a capacitor as a filter (CFLT) on MFLT and PFLT pins. but the app note did not speak about how much this capacitor can be large!? the test results show a 1uF as CFLT. is it possible to using a large CFLT and how to calculate the proper value for it?
2. for input ac decoupling capacitors series with INPA and INPB pins, if i want to operate with a low frequency such as 20 Hz I have to use a large capacitor in range of 22u to 47u. according to the desire frequency range of operation, the circuit must be work till 50 Mhz so we have to use high speed op amps as analog front end circuits. the question is which high speed op amps can and how drive this large capacitor as a load?
also if I going to select a FET input high speed op amp with very large input impedance, I can design an ac coupling circuit with small value capacitor with Mega Ohm range resistor but choosing a larger resistor make some issues with parasitic characteristics and thermal noise and so on... so what cand we do about choosing the proper high speed op amp for analog front end of AD8302 if it works in a wide range frequency included the low one?
3. how much large the termination resistor on the signal side of the input coupling capacitor cab be choose?
4. also I have question about putting a 90 degree phase shifter that data sheet recommended in one input to make a better reading of phase differences. you know almost of the phase shifter operation related to frequency. you consider a active phase shifter based on an op amp. if you choose a fix RC and change the input frequency, then you have a different amount of phase shift.
so if I want to scan the freqency range from 20 Hz to 50 MHz, What phase shifter or programmable phase shifter circuit do you recommend to have a fix 90 degree phase shift in a range?