Dear RF experts,
We are using both the parts for a wide-bandwidth PLL design (VCO 14GHz with external frequency divider by 32, KVCO 1GHz/V, VCO modulation bandwidth exceeding 1GHz, loop filter op-amp THS4304 with 3GHz small-signal bandwidth, loop filter synthesized from ADIpllsim tool). We aim for a bandwith of 50MHz or higher but only get to 30MHz in measurements. Higher bandwidth setting makes the loop unstable. Upon many investigations, it is still mysterious to us why the BW could not go higher and we come up with some questions:
- What are the rise/fall times and the propagation delay (the time it takes for digital pulses appear with respect to the REF and VCO inputs) of the PFDs?
- Is there a way to include these parts in transient simulation with our loop filter and VCO?
Many thanks and regards,
[edited by: anhchu_ite at 10:24 AM (GMT 0) on 27 Nov 2019]