Dear RF experts,
We are using both the parts for a wide-bandwidth PLL design (VCO 14GHz with external frequency divider by 32, KVCO 1GHz/V, VCO modulation bandwidth exceeding 1GHz, loop filter op-amp THS4304 with 3GHz small-signal bandwidth, loop filter synthesized from ADIpllsim tool). We aim for a bandwith of 50MHz or higher but only get to 30MHz in measurements. Higher bandwidth setting makes the loop unstable. Upon many investigations, it is still mysterious to us why the BW could not go higher and we come up with some questions:
- What are the rise/fall times and the propagation delay (the time it takes for digital pulses appear with respect to the REF and VCO inputs) of the PFDs?
- Is there a way to include these parts in transient simulation with our loop filter and VCO?
Many thanks and regards,
Unfortunately you didn't include a schematic and part numbers / values (VCO, loop filter, etc) so it's a bit difficult to provide a clear answer to this one. If you're not comfortable sharing this in a public forum let me know and I'll contact you directly. It sounds like you are nesting two (2) PLL's where one serves as a tune-able reference for another to achieve improved channel spacing / resolution while operating in integer mode/ A similar concept is shown in the applications section of the datasheet for the HMC830 integrated VCO / PLL product. What's confusing is the use of both the HMC439 and HMC3716 as opposed to simply using (2) HMC3716's which would offer the same noise performance but a little better ESD protection with a smaller total footprint. It suggests that the resistors on the outputs of the HMC439 may not be following the recommended values as these are not accessible on the HMC3716. The loop bandwidth that can be realistically achieved is typically limited to 1% of the GBW of the op amp being used.
As far as modelling your synthesizer in ADISimPLL I believe it can be achieved but it will likely take some creativity and a model based on the results of 'sub-models' will likely be required so it will be an iterative process. It will also likely require multiple models
ADISimPLL does not contain any 3rd party op amps however it does allow the user to create their own 'custom op amp' model which may be of some benefit as far as modeling it's impact on noise. Unfortunately the op amp models do not include the gain bandwidth parameter and I don't believe that ADISimPLL currently fully takes this into account so for the case of very wide loop bandwidths it may show that you can achieve it but it may not be realizable on the bench. We are aware of this limitation and do have a long term desire to add this feature.
Assuming your using a nested PLL configuration, you'll need to create a 'custom reference' using the properties of your inner loop (tunable reference). Unfortunately you'll need to make multiple custom references that operate at various frequencies in order to accurately create the final model as the 'custom reference' models only include basic parameters (no sensitivity or tuning properties). These 'custom references' could then be used when modelling the outer loop (a separate model). Note that the latest version of ADISimPLL includes both the HMC439 and HMC3716 and active loop filters appropriate for these devices.
If the 14 GHz VCO you're using isn't included in one of the default libraries you can create a 'custom VCO' for it as well and include it in the final model.
I've attached an image showing the recommended resistor values for optimal performance of the HMC439 as well as a link to my PFD FAQ which may be of some use.
ADI Phase Frequency Detector FAQ:
Thanks a lot for your useful reply, especially on the tips of using ADIsimPLL and the nested PLL circuit. We actually have 2 PLL versions. An old version used HMC439 and a newer version use HMC3716. The VCO is a custom-made one, with parameters as in my last question. Both PLLs are simple integer-N PLL and they are not nested PLL.
Your point on the realistically achieved BW at 1% of the op-amp BW seems very relevant to our case: op-amp GBW 3GHz, and max BW 30MHz. Could you elaborate on this? I normally think a GBW of 2-3 times the non-dominant poles (so 20-30 times the PLL BW) is enough to not degrade the phase margin. Is the 1% limit an experimental figure, or is there a calulation/theory behind it? Even better if you could suggest an op-amp suitable for our 50MHz PLL BW target.
Our concern is that the propagation delay from the PFDs could be large, which degrade the phase margin. Have you any comments on this?
Our last point: Have you simulation models, for example ibis, for the PFDs, so we could perform transient simulation of our PLLs, either in ADS or Cadence?
For your reference, I attach the schematic taken from ADIpllSim tool.
My comment regarding 1% is just a conservative rule of thumb that I use. It's possible to achieve loop bandwidths that are greater than 1% of the 3dB GBW product. The AD8065 or LT6200 are a couple of op amps you might consider. Unfortunately we do not have propagation delay data or IBIS models for these PFD's.