HMC3716 and HMC439 propagation delay

Dear RF experts,

We are using both the parts for a wide-bandwidth PLL design (VCO 14GHz with external frequency divider by 32, KVCO 1GHz/V, VCO modulation bandwidth exceeding 1GHz, loop filter op-amp THS4304 with 3GHz small-signal bandwidth, loop filter synthesized from ADIpllsim tool). We aim for a bandwith of 50MHz or higher but only get to 30MHz in measurements. Higher bandwidth setting makes the loop unstable. Upon many investigations, it is still mysterious to us why the BW could not go higher and we come up with some questions:

- What are the rise/fall times and the propagation delay (the time it takes for digital pulses appear with respect to the REF and VCO inputs) of the PFDs? 

- Is there a way to include these parts in transient simulation with our loop filter and VCO?

Many thanks and regards,

Anh



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[edited by: anhchu_ite at 10:24 AM (GMT 0) on 27 Nov 2019]
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  • +1
    •  Analog Employees 
    on Nov 27, 2019 3:00 PM

    Hi Anh, 

    Unfortunately you didn't include a schematic and part numbers / values  (VCO, loop filter, etc) so it's a bit difficult to provide a clear answer to this one. If you're not comfortable sharing this in a public forum let me know and I'll contact you directly. It sounds like you are nesting two (2) PLL's where one serves as a tune-able reference for another to achieve improved channel spacing / resolution while operating in integer mode/ A similar concept is shown in the applications section of the datasheet for the HMC830 integrated  VCO / PLL product. What's confusing is the use of both the HMC439 and HMC3716 as opposed to simply using (2) HMC3716's which would offer the same noise performance but a little better ESD protection with a smaller total footprint. It suggests that the resistors on the outputs of the HMC439 may not be following the recommended values as these are not accessible on the HMC3716. The loop bandwidth that can be realistically achieved is typically limited to 1% of the GBW of the op amp being used. 

    As far as modelling your synthesizer in ADISimPLL I believe it can be achieved but it will likely take some creativity and a model based on the results of 'sub-models' will likely be required so it will be an iterative process. It will also likely require multiple models 

    ADISimPLL does not contain any 3rd party op amps however it does allow the user to create their own 'custom op amp' model which may be of some benefit as far as modeling it's impact on noise. Unfortunately the op amp models do not include the gain bandwidth parameter and I don't believe that ADISimPLL currently fully takes this into account so for the case of very wide loop bandwidths it may show that you can achieve it but it may not be realizable on the bench. We are aware of this limitation and do have a long term desire to add this feature. 

    Assuming your using a nested PLL configuration, you'll need to create a 'custom reference' using the properties of your inner loop (tunable reference). Unfortunately you'll need to make multiple custom references that operate at various frequencies in order to accurately create the final model as the 'custom reference' models only include basic parameters (no sensitivity or tuning properties).  These 'custom references' could then be used when modelling the outer loop (a separate model). Note that the latest version of ADISimPLL includes both the HMC439 and HMC3716 and active loop filters appropriate for these devices. 

    If the 14 GHz VCO you're using isn't included in one of the default libraries you can create a 'custom VCO' for it as well and include it in the final model. 

    I've attached an image showing the recommended resistor values for optimal performance of the HMC439 as well as a link to my PFD FAQ which may be of some use. 

    ADI Phase Frequency Detector FAQ: 

    https://ez.analog.com/rf/w/documents/9627/faq-hmc-phase-frequency-detectors

    Best Regards, 

    Marty

Reply
  • +1
    •  Analog Employees 
    on Nov 27, 2019 3:00 PM

    Hi Anh, 

    Unfortunately you didn't include a schematic and part numbers / values  (VCO, loop filter, etc) so it's a bit difficult to provide a clear answer to this one. If you're not comfortable sharing this in a public forum let me know and I'll contact you directly. It sounds like you are nesting two (2) PLL's where one serves as a tune-able reference for another to achieve improved channel spacing / resolution while operating in integer mode/ A similar concept is shown in the applications section of the datasheet for the HMC830 integrated  VCO / PLL product. What's confusing is the use of both the HMC439 and HMC3716 as opposed to simply using (2) HMC3716's which would offer the same noise performance but a little better ESD protection with a smaller total footprint. It suggests that the resistors on the outputs of the HMC439 may not be following the recommended values as these are not accessible on the HMC3716. The loop bandwidth that can be realistically achieved is typically limited to 1% of the GBW of the op amp being used. 

    As far as modelling your synthesizer in ADISimPLL I believe it can be achieved but it will likely take some creativity and a model based on the results of 'sub-models' will likely be required so it will be an iterative process. It will also likely require multiple models 

    ADISimPLL does not contain any 3rd party op amps however it does allow the user to create their own 'custom op amp' model which may be of some benefit as far as modeling it's impact on noise. Unfortunately the op amp models do not include the gain bandwidth parameter and I don't believe that ADISimPLL currently fully takes this into account so for the case of very wide loop bandwidths it may show that you can achieve it but it may not be realizable on the bench. We are aware of this limitation and do have a long term desire to add this feature. 

    Assuming your using a nested PLL configuration, you'll need to create a 'custom reference' using the properties of your inner loop (tunable reference). Unfortunately you'll need to make multiple custom references that operate at various frequencies in order to accurately create the final model as the 'custom reference' models only include basic parameters (no sensitivity or tuning properties).  These 'custom references' could then be used when modelling the outer loop (a separate model). Note that the latest version of ADISimPLL includes both the HMC439 and HMC3716 and active loop filters appropriate for these devices. 

    If the 14 GHz VCO you're using isn't included in one of the default libraries you can create a 'custom VCO' for it as well and include it in the final model. 

    I've attached an image showing the recommended resistor values for optimal performance of the HMC439 as well as a link to my PFD FAQ which may be of some use. 

    ADI Phase Frequency Detector FAQ: 

    https://ez.analog.com/rf/w/documents/9627/faq-hmc-phase-frequency-detectors

    Best Regards, 

    Marty

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