We are thinking in migrating a current design from HMC767 to avoid excesively low tning voltages to get 8GHz output frequency. Our idea is to use HMC765 instead but phase noise floor degradation seems to be expected. My questions are:
1. it is a real risk on locking HMC767 around such a low tuning voltage (around 1.1Volts to get 8GHz output frequency) or we can go on with original design based on that reference?
2. If move to HMC765, can we take the advantage of auxiliary DC circuitry coming from previous design: HMC976 and HMC860, instead of using those devices recommended at HMC765 datasheet: 3 units of LP5900-3_3V and 2 units of LP3878MR-ADJ (both VCO models seems to have similar current consumption)
3. That 4dB PN degradation from HMC765 higher PN floor is unavoidable to be suffered at 8GHz output (we are going to use PLL as integer with up to 100MHz FPD)
4. Any other recommendation to get the closest possible performance than that obtained previously with HMC767?
A lot of questions... Thanks in advance to help me finding the best possible design at a new frequency.
You didn't mention your application or the loop BW you're using so the following is assuming that REF / PFD, Icp etc. must remain as they are.
1) I don't recommend attempting to use the HMC767…
1) I don't recommend attempting to use the HMC767 for an 8.0 GHz application. Over process & temperature at 8 GHz, Vtune could drop well below 1.1 Volts which will result in increased spurious in fractional mode due to the proximity to low rail, inability to lock depending on op amp characteristics (would need a rail-rail op amp like the ADA4084-1 or ADA4625).
2) Yes I would recommend you use the HMC976 and HMC860 LDO's used with the HMC767 as a minimum. Depending on the ampacity, spurious and isolation needs of your application you may be able to get away with a single HMC1060 (Using VR4 for the VCO and the remainder of outputs to isolate analog / digital and LS / CP circuits. The HMC1060 includes a PTAT circuit which compensates for voltage change over temp.
3) Not sure what the question is here.
4) The HMC834 would be a good option to consider if the VCO PN performance is acceptable (-100 dBc @ 100kHz at 8 GHz)
5) The ADF5356, particularly for an integer mode application might be considered. VCO PN is about -108 dBc @ 100kHz at 8 GHz). Like the HMC765 it does not include sweep functions so I'm guessing these aren't needed. Although the FOM is only about 1 dB better it has a few attractive features. The ADF5356 uses a passive loop which will eliminate the need for an op amp reducing cost and saving board space which means there's more room to improve the layout for better isolation potentially. It also offers multiple outputs which may be helpful.
5) The ADF5610 has a similar FOM as the HMC767 with similar VCO performance but it covers a total of 8 octaves. This part has the flexibility to work across multiple platforms both today and in the future which may provide some economy of scale. It too utilizes a passive loop filter and only loses about 1 dB of phase noise performance if the HMC1060 is used instead of the LT3042 and LT3045 that are recommended. Jitter of 40 fs can be achieved at 8 GHz (as well as many other frequencies) and total power consumption is only 815 mW typically but can be configured to use less than 700 mW at a cost of 1 to 2 dBc/Hz of phase noise performance.
6) The ADF4372 has a FOM of -234 and operates in a manner similar to the ADF5610 but the VCO PN is a bit higher.
7) Lots of discrete PLL / VCO options that can provide the same or better PLL / VCO PN performance as you currently have with the HMC767.
Thank you very much for your help.
I'm sorry for not including more details...
Indeed you were right in most of your guessings:
· I don't need to implement any sweep
· I'm going to use them in integer mode
· Application of use is quite restrictive in terms of spectral purity and PN mask requirements are: -90dBc/Hz @ 1kHz ; -100dBc/Hz @ 10kHz and -105dBc/Hz @ 100kHz offsets
· The loop BW at original design (using HMC767) were closed around 100kHz
We have checked ADF5356 at some of our designs but getting PN performance not so good as HMC767 for similar output frequencies. We have not used the other alternatives you recommended, but, with such a demanding PN requirement, I think that some of them would not be suitable (like HMC834).
I'm sure discrete solutions could provide good performance will have a look.
Thanks again for your support, any further recommendation will be appreciated.
Sounds like your best bet will be the new ADF5610 or ADF4371 / 72 as both meet the phase noise requirements as long as you use a good reference (modeled in ADISimPLL to confirm). At 100kHz loop bandwidth, -108 dBc/Hz is easily achieved on either of these at devices.
The ADF5610 offers fast lock times with auto-cal enabled (111 us) but at this loop BW you won't get much more margin for noise by pushing the loop bandwidth out further except at offsets between 10k and 100k due to the modest FOM.The ADF4371 achieves similar performance with a 100kHz loop but due to the -234 dBc/Hz FOM the loop BW can be pushed out much further to provide -110 dBc/Hz at a LBW of 200kHz and better than -113 dBc/Hz if you push the loop BW out to 500 kHz to 1MHz. The only negative is that with auto-cal enabled the settling time is 3 ms vs 111 us for he ADF5610. Of course you can use a LUT with either one of these parts to allow lock times of 10 us.
The ADF4372 is similar to the ADF4371 but it doesn't include the output multiplier to play from 16 GHz to 32 GHz.
ADISimPLL v5.10.03 can be used to model these. See attached
Simulated ADF4371 REF_100MHz_8 GHz Rename dotPLL.pdf
Simulated ADF5610 REF_100MHz_8 GHz Rename dotPLL.pdf
Thank you again for the support.
Time to lock is not critical in the application but we need to keep PN at minimum with some margin for real implementation.
Unfortunately, I can't open pdfs you attacdhed at your post.
I have a different challenge now, to get LO signal to 32GHz with similar PN requirements: -72 dBc/Hz @100Hz; -82 dBc/Hz @ 1kHz; -92 dBc/Hz @ 10kHz; -102 Bc/Hz @ 100kHz; -112 dBc/Hz @ 1MHz. My first try was to use ADF4371 to get 16GHz signal and then multiply that by 2 discounting 6dB of PN. But can't reach objective PN at 100kHz and 1MHz to overcome that multiplication... May you have any other recomendation to get so demanding PN requirement at so high freq?..
Thanks in advance.
Download and save the attachments first then you must rename them to *.pll in order to open with ADISimPLL. EZ would not allow me to upload *.pll files so I renamed them as *.pdf files so that I could add them to the post.
As far as a 32 GHz LO it looks like you can get there (barely) using the ADF5610 and multiply up, may want to use an exceptionally good reference for margin at 100 Hz. Could also consider multiplying up a source that will allow you to meet these requirements (OCXO or ZCOMM has an 8 GHz CRO & DRO that barely will allow you to meet this after multiplying up). You can check out our multiplier lineup on analog.com in the RF/ Microwave section.
Could also use frequency translation to up convert or use a translation loop (offset loop architecture) at 8 GHz to improve the phase noise then multiply up.
Thank you again for all your support.
I didn't know what to do to open your simulations, thanks.
Will take into account your recommendations for 32GHz PLO. Actually some of your commentaries were allready at my preliminary design.
Could you share with me any web link to learn more about that frequency translation method or translation loop, I'm not familar with it and sounds interesting.
Thanks in advance