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ADF4218L Power-Up Sequence

Our team is planning on using the ADF4218L on one of our products. Reading through the AskTheCommunity questions there are references on the ADF4212L about clearing all bits in the IF R Counter Latch register and RF R Counter Latch register immediately after power-up, prior to programming the desired commands. Does this same recommendation applies to the ADF4218L? And if it does is it just registers 0x0 and 0x2 that need to be cleared after power-up or do all four registers (0x0, 0x1, 0x2, x03) should be cleared after power-up prior to programming the desired commands?

ADF4212 conversations referenced above:
https://ez.analog.com/rf/f/q-a/71544/adf4212l-power-up-sequence-through-rate-2/
https://ez.analog.com/rf/f/q-a/75846/adf4212l-power-up-sequence-through-rate

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  • I received some information back from ADI indicating that ADF4218L has the same “test bits” as the ADF4212 but they did not think the information above was necessary under normal operation.

    The way I interpreted this was that the references for the ADF4212L were “abnormal” cases where the power supply sequencing was too slow. 

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  • I received some information back from ADI indicating that ADF4218L has the same “test bits” as the ADF4212 but they did not think the information above was necessary under normal operation.

    The way I interpreted this was that the references for the ADF4212L were “abnormal” cases where the power supply sequencing was too slow. 

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