We know the ADISimPLL can help us to design the loop filter for Charge Pump coutput PLL, but are there any guides or softwares to help/tell us how to design a Loop filter
for the Hik mode of HMC703 or ADF5610 ?
Unfortunately, the ability to use an active loop (required for HiK mode) in ADISimPLL was accidentally removed from many of our integrated VCO / PLL products. We hope to restore this capability soon but in the mean time we can apply we know about loop design and the parameters that impact the loop filter and implement a work around. Please bear in mind that the work around may not be as quite as accurate as but it should be close enough that you can get something working. It may require an iteration or two or tweaking on the bench to optimize. I used the techniques outlined below during the development of the ADF5610 as there was no ADISimPLL model so I know they work however I have not used them with HiK mode.
The ability to simulate a loop with HiK mode was never included in the HMC5610 ADISimPLL model but there may be a way to estimate the loop performance (at least for loop bandwidth).