How to design the loop filter for HMC703 or ADF5610 which working at Hik mode.

Hi, ADI 

We know the ADISimPLL can help us to design the loop filter for Charge Pump coutput PLL, but are there any guides or softwares to help/tell us how to design a Loop filter

for the Hik mode of HMC703 or ADF5610 ?

Thanks~

Parents
  • +1
    •  Analog Employees 
    on Nov 12, 2019 8:15 PM

    Hi there,

    Unfortunately, the ability to use an active loop (required for HiK mode) in ADISimPLL was accidentally removed from many of our integrated VCO / PLL products. We hope to restore this capability soon but in the mean time we can apply we know about loop design and the parameters that impact the loop filter and implement a work around. Please bear in mind that the work around may not be as quite as accurate as but it should be close enough that you can get something working. It may require an iteration or two or tweaking on the bench to optimize. I used the techniques outlined below during the development of the ADF5610 as there was no ADISimPLL model so I know they work however I have not used them with HiK mode.

    The ability to simulate a loop with HiK mode was never included in the HMC5610 ADISimPLL model but there may be a way to estimate the loop performance (at least for loop bandwidth).

    • To allow use of an active loop and access to several good op amp choices use the HMC704 as the base part for the model. 

    • Next, create a 'custom' VCO based on the performance and temperature that you plan to operate at. This would be the most accurate approach as you can use the measured data shown in the plots of the datasheet. If your frequency range will utilize both VCO cores of the ADF5610, you'll need to create two custom VCO models, one for each core. The key regions to evaluate the loop bandwidth (LBW) and phase margin will be the band edges and the region where the cores overlap.

    • Alternatively, if the frequency range you need is narrow you could search for VCO's that have similar tuning sensitivity at the same frequency as those you intend to use for your application using the ADF5610. Figure 10 of the latest ADF5610 datasheet shows that the tuning sensitivity range is roughly 110 MHz/V to 70MHz/V for the lower VCO core (7.3 G to ~ 10.3 GHz) and 140MHz/V to 90MHz/V (10.4GHz to 14.6 GHz) for the upper VCO core. Due to the narrow bandwidth of the devices that are going to be a better match (HMC5xx and HMC116x series for example) you will need to duplicate your efforts across several models if your bandwidth is very wide and to maintain a close relationship between frequency and tuning sensitivity between the model you select and ADF5610. I believe that while this simplifies the initial effort, ultimately this will be more work than creating a couple of good custom VCO models.

    • Since we know that LBW is roughly proportional to Icp, depending on the HiK mode you plan to use, you can estimate the LBW by evaluating your loop at an Icp level that is integer value less than that expected in HiK mode and multiply the resulting LBW by the integer value to estimate the LBW in HiK mode.

    • To get a better understanding of what improves loop stability as Icp is varied (in ADISimPLL) track design frequency / VCO core, Kv, Icp, LBW, phase margin (PM) and the loop component values. It may be helpful to start with an Icp value that can be doubled in the existing ADISimPLL model (1.24mA) so that you can see how the loop components impact PM as Icp is doubled. The trend would be expected to continue when you implement the physical design and HiK mode. You will tweak these component values to minimize the PM variation as you optimize the model. I would design the final loop however, as close to the maximum Icp or at the maximum Icp to minimize the error when you implement HiK mode. 

    • Example: Our application will use max charge pump current + HiK mode for a total of 6mA of charge pump current. The HMC704 ADISimPLL model does not include a HiK option so we will model our loop using 2mA or 1/3 of the desired charge pump current. We know that with 6mA we hope to achieve a 120kHz LBW so for our model we will aim for 1/3 of this or 40kHz. Once the loop has been synthesized by specifying PM and LBW and we are happy with the response, specify the loop by 'components' in ADISimPLL (can opt to use standard values that are closest to what was shown to achieve the 40kHz LBW if desired).

      1. Next, with the loop still specified by components',  increase the LBW to 2.54mA. Tweak the component values as needed so that PM remains as stable as possible as you vary Icp between 2.0mA and 2.54mA. If a 3:1 ratio proves to difficult to realize a stable loop at 6mA then you may need to design closer to the max Icp value.

    • Note that PM does not vary in the same manner / magnitude (to see this, use the same initial LBW and PM and compare starting with a low Icp and doubling vs starting a design with a higher Icp and reducing by 50%).

    • Don’t forget to verify the performance of your loop on the other VCO core if applicable.

    Best Regards,

    Marty

Reply
  • +1
    •  Analog Employees 
    on Nov 12, 2019 8:15 PM

    Hi there,

    Unfortunately, the ability to use an active loop (required for HiK mode) in ADISimPLL was accidentally removed from many of our integrated VCO / PLL products. We hope to restore this capability soon but in the mean time we can apply we know about loop design and the parameters that impact the loop filter and implement a work around. Please bear in mind that the work around may not be as quite as accurate as but it should be close enough that you can get something working. It may require an iteration or two or tweaking on the bench to optimize. I used the techniques outlined below during the development of the ADF5610 as there was no ADISimPLL model so I know they work however I have not used them with HiK mode.

    The ability to simulate a loop with HiK mode was never included in the HMC5610 ADISimPLL model but there may be a way to estimate the loop performance (at least for loop bandwidth).

    • To allow use of an active loop and access to several good op amp choices use the HMC704 as the base part for the model. 

    • Next, create a 'custom' VCO based on the performance and temperature that you plan to operate at. This would be the most accurate approach as you can use the measured data shown in the plots of the datasheet. If your frequency range will utilize both VCO cores of the ADF5610, you'll need to create two custom VCO models, one for each core. The key regions to evaluate the loop bandwidth (LBW) and phase margin will be the band edges and the region where the cores overlap.

    • Alternatively, if the frequency range you need is narrow you could search for VCO's that have similar tuning sensitivity at the same frequency as those you intend to use for your application using the ADF5610. Figure 10 of the latest ADF5610 datasheet shows that the tuning sensitivity range is roughly 110 MHz/V to 70MHz/V for the lower VCO core (7.3 G to ~ 10.3 GHz) and 140MHz/V to 90MHz/V (10.4GHz to 14.6 GHz) for the upper VCO core. Due to the narrow bandwidth of the devices that are going to be a better match (HMC5xx and HMC116x series for example) you will need to duplicate your efforts across several models if your bandwidth is very wide and to maintain a close relationship between frequency and tuning sensitivity between the model you select and ADF5610. I believe that while this simplifies the initial effort, ultimately this will be more work than creating a couple of good custom VCO models.

    • Since we know that LBW is roughly proportional to Icp, depending on the HiK mode you plan to use, you can estimate the LBW by evaluating your loop at an Icp level that is integer value less than that expected in HiK mode and multiply the resulting LBW by the integer value to estimate the LBW in HiK mode.

    • To get a better understanding of what improves loop stability as Icp is varied (in ADISimPLL) track design frequency / VCO core, Kv, Icp, LBW, phase margin (PM) and the loop component values. It may be helpful to start with an Icp value that can be doubled in the existing ADISimPLL model (1.24mA) so that you can see how the loop components impact PM as Icp is doubled. The trend would be expected to continue when you implement the physical design and HiK mode. You will tweak these component values to minimize the PM variation as you optimize the model. I would design the final loop however, as close to the maximum Icp or at the maximum Icp to minimize the error when you implement HiK mode. 

    • Example: Our application will use max charge pump current + HiK mode for a total of 6mA of charge pump current. The HMC704 ADISimPLL model does not include a HiK option so we will model our loop using 2mA or 1/3 of the desired charge pump current. We know that with 6mA we hope to achieve a 120kHz LBW so for our model we will aim for 1/3 of this or 40kHz. Once the loop has been synthesized by specifying PM and LBW and we are happy with the response, specify the loop by 'components' in ADISimPLL (can opt to use standard values that are closest to what was shown to achieve the 40kHz LBW if desired).

      1. Next, with the loop still specified by components',  increase the LBW to 2.54mA. Tweak the component values as needed so that PM remains as stable as possible as you vary Icp between 2.0mA and 2.54mA. If a 3:1 ratio proves to difficult to realize a stable loop at 6mA then you may need to design closer to the max Icp value.

    • Note that PM does not vary in the same manner / magnitude (to see this, use the same initial LBW and PM and compare starting with a low Icp and doubling vs starting a design with a higher Icp and reducing by 50%).

    • Don’t forget to verify the performance of your loop on the other VCO core if applicable.

    Best Regards,

    Marty

Children
No Data