We have the LTC6946 designed into a product and have shipped >30 units over the last couple of years. In a recent batch of products we have noticed that the PFD frequency leaks into the PLL output much more in LTC6946 devices bought recently compared to ones from earlier batches i.e a couple of years ago.
We are sure it is the device as we have taken an old LTC6946 device from a working board and replaced on a non working new board and we can see the problem follows the device, so rules out our PCB's
This is a working device - old device from a couple of years ago..
And with the device replaced with a new device
and another new device on another board..
The spur frequency is 220kHz which is our PFD.
We are a little stuck as to what the problem may be.
This is the schematic of the PLL
The reference is not particularly clean as it comes from an FPGA, but the first plot you see is sufficiently good performance.
Something appears to have changed with the devices, but there is also the possibility we are doing something wrong which makes our design susceptible/sensitive to small changes.
Is there anything you think we could do to resolve the PFD leakage into the output? and is this a problem seen before? and have there been any revisions of the hardware over the last few years?
Thanks for the description. I'd like to understand your loop filter a little more. As these values are much different than we would recommend using the PLLWizard tool. Do you recall why you used these values? Can you send over the register settings you use for the LTC6946-2? I'm particularly interested in the registers CP and RDIV.
From the schematic and your description, I see the following fref=50MHz, fpfd = ~220kHz, rfout =860M-900M (which implies your using an output divider of 5, correct?)
Below is the loop filter I generate based on what I understand about your setup. (Rz=173 ohms, Ci=828nF, Cp=67nF). I used the Icp=11.2mA for this loop filter.
please note, Below is the loop filter I generate based on what I understand about your setup. (Rz=173 ohms, Ci=828nF, Cp=67nF). I used the Icp=11.2mA for this loop filter. I had an error in my first reply
Thanks for the reply, these are the settings we are currently using
Thanks for the settings.
In register H04, the RD value =130, but the comment says R=240. If your reference frequency is 50MHz, then the fpfd is around 384.6kHz (not 220kHz as shown in your plots). I'm guessing the comment in the schematic about the 50MHz reference is not correct? 220kHz * 130 (Rdiv) = 28.6MHz. Is your reference frequency 28.6MHz?
I wasn't sure which frequency plan to design a loop filter for, so I provided solutions for both ref & pfd frequency combinations. I assumed a fairly noisy reference in this design, since you mentioned this was coming from a FPGA. Let me know if this helps.
Here is the loop filter design for 50M reference/130 = 384.6kHz pfd
and for 28.6M reference/130 = 220kHz pfd
Thanks, we tried your first set of loop filter values..
Rz=173 ohms, Ci=828nF, Cp=67nF). I used the Icp=11.2mA for this loop filter. I had an error in my first reply
(As a note, our reference is 50MHz fixed. We have been experimenting with different R divider values, so it may have changed. Apologies for this. The register values provided is what we are using currently)
This loop filter gave a good result with a newly purchased batch of devices (from Digikey) - see below..
Interestingly with this new chip replaced with one of the LTC6946-2 devices from the failing batch of boards, we got this.. so only the device changed (unsoldered and then soldered) between these two plots - everything else (including loop filter) is the same
We are trying to find out the exact origin and batch of these devices, but for now, we are going to replace the devices with newer ones. Can you think of a reason why we would see such a difference?