I am a bit confused about the FLTR capacitor on the LTC5596.
The LT5596 datasheet states:
FLTR Interface (Pin 3):
"Suitable capacitance values are in the range from 10pF up to 1nF, but the total of feedback and load capacitance (from OUT to signal ground) should not exceed 1nF. Larger capacitance values may result in instability of the output driver."
The DC2870A (Linduino Shield 100MHz to 40 GHz RMS Power Detector) schematic shows a 0.01uF (10nF) capacitor between the FLTR pin and OUT.
This would appear to violate the maximum FLTR capacitor which is allowed between FLTR and OUT.
- Could Analog confirm whether there is an error in the datasheet or an error in the DC2870A schematic? (i.e what is the largest capacitor I can use?)
- Also, does Analog have data on the effect on rise / fall time with different capacitor values?
Thanks for the help.
[edited by: JValeriani at 7:44 PM (GMT 0) on 10 Oct 2019]