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LTC5596 FLTR capacitor effect

Hello.

I am a bit confused about the FLTR capacitor on the LTC5596.

The LT5596 datasheet states:

FLTR Interface (Pin 3):

"Suitable  capacitance  values  are  in  the  range  from  10pF up to 1nF, but the total of feedback and load capacitance (from  OUT  to  signal  ground)  should  not  exceed  1nF. Larger capacitance values may result in instability of the output driver."

The DC2870A (Linduino Shield 100MHz to 40 GHz RMS Power Detector) schematic shows a 0.01uF (10nF) capacitor between the FLTR pin and OUT.

This would appear to violate the maximum FLTR capacitor which is allowed between FLTR and OUT.

  1. Could Analog confirm whether there is an error in the datasheet or an error in the DC2870A schematic? (i.e what is the largest capacitor I can use?)
  2. Also, does Analog have data on the effect on rise / fall time with different capacitor values? 

Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/5596f.pdf

DC2870A: https://www.analog.com/media/en/technical-documentation/eval-board-schematic/710-DC2870A_REV01_PCA_SCHEMATIC.pdf

Thanks for the help.



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[edited by: JValeriani at 7:44 PM (GMT 0) on 10 Oct 2019]