I've been studying the datasheet for ADA4961 and I see that there is not timing specifications defined (at least that I found) for the device when in Parallel mode.
What is the setup and hold time for the ADA4961 in parallel mode with respect to the latch signal?
I'm working on the answer to your question, and hope to reply early next week. As you noted, the timing config for parallel mode isn't very clear in our datasheet, and will require input from our design team.
The ADA4961 has the same parallel timing as our ADL5205, which has more detail on timing in the datasheet, pg 5. Let me know if you have further questions.
Thanks for finding this for me. I admit, that Figure 4 in the attached picture (ADL5205 datasheet), should really be fixed. It fails to reference Tds (which I'm currently assuming is the setup time for the parallel mode despite this error). Also, it looks like the diagram is drawn to show the Latch Signals as a low asserted signal, which contradicts the writing below in the theory of operation.
Could you pass on these comments and suggest something similar be added to ADA4961?