ADA4961 Parallel mode latch setup and hold time

I've been studying the datasheet for ADA4961 and I see that there is not timing specifications defined (at least that I found) for the device when in Parallel mode. 

What is the setup and hold time for the ADA4961 in parallel mode with respect to the latch signal?

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    Thanks for finding this for me. I admit, that Figure 4 in the attached picture (ADL5205 datasheet), should really be fixed. It fails to reference Tds (which I'm currently assuming is the setup time for the parallel mode despite this error). Also, it looks like the diagram is drawn to show the Latch Signals as a low asserted signal, which contradicts the writing below in the theory of operation.

    Could you pass on these comments and suggest something similar be added to ADA4961?

    Thanks!

    Mark

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