I'm struggling a bit with the EVAL-HMC767LP6CE around the reference divider 'R' and the lock detect output.
In general, I find setting the R divider to 2 or anything other than 1 the charge pump output rails pushing the VCO to the lowest freq... I have even redesigned the loop filter for the appropriate phase detector comparison frequency. When I try to observe the reference divider output on the LD_SDO pin I only see an output when R=1 but setting it to other than 1 there is no output on the LD_SDO pin. I would like to work in integer mode with an R divider.
Putting that aside, in fractional mode, when I use a 10 MHz reference with R=1 I cannot get the lock detect to assert itself, even though the output looks to be locked. I have adjusted the loop filter accordingly.
As a side note, using the HMC PLL VCO Evaluation Software V3280 and selecting HMC767 fractional default register settings, register 07h looks different than what the Users Guide (140-00074-00 revA PLLs WITH INTEGRATED VCO - MICROWAVE APPLICATIONS PRODUCT & OPERATING GUIDE - COVERS HITTITE PART NUMBER HMC767LP6CE, HMC769LP6CE, HMC778LP6CE) calls for default values. For example [10:3] calls for 12d but the tool programs it to 11d when default values are loaded.
Let's work through each issue and see if we can get it to lock.
1) I suspect that the reason the part rails when you change the R divider value is that you aren't "re-training" the LD window. Each…
1) I suspect that the reason the part rails when you change the R divider value is that you aren't "re-training" the LD window. Each time the R divider is changed you need to toggle REG 0x07. Hopefully this will correct this problem.
2) Based on your ADISimPLL file you are simulating 9.37 GHz using a 10 MHz PFD frequency and you did correctly state that this will be fractional mode. Just be sure that your ADISimPLL was done using fractional mode or the in-band phase noise will be 2 to 3 dBc/Hz better than you will realize.
3) In your ADISimPLL file you did not enable lock detect (enable 'Digital Filter' under LD frame on the dialog box where you select the PLL chip). Use 'Edit' to edit the 'PLL configuration', ADISimPLL simulation and enable LD as mentioned above and when you get to the last dialog box be sure to check "Lock Detect Circuit" under "If you wish ADISimPLL to reset any parameters as if this were a new design check the items below", then click "Finish". Perhaps ADISimPLL is retaining info from a previous simulation that did lock; this should reset it. Could also create a completely new file.
4) Using ADISimPLL v5.00.03 my simulation shows that your it does not lock using this loop.
5) For an active loop typically would set the Icp Offset to use 'Source CP Offset' vs 'Sink' but this shouldn't impact LD.
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