Customer using ADF5356, but I think the issue is the same for all of ADF4355, ADF4356, ADF5355, ADF5356... maybe others.
Don't think any of these details matter: f(REF) = f(PFD) = 20 MHz; f(VCO) = ~3.7 GHz; using RFoutB path to get x2 out f(RF) = 7.4 GHz.
Make continual phase adjustments of output without triggering a loss of lock. As I understand it, adjustment occurs in the ΣΔ modulator and is adjusted with respect to f(REF), but in the system app they'd effectively be looking to control phase adjustment using an [external] phase comparison to an identically-generated output on a similar synth using the same f(REF).
Instructions pertaining to use of the phase setting in Reg 3 suggest that a write to Reg 0 is necessary to effect the phase adjustment. Customer also confirms that by writing to Reg 3 alone they saw no phase adjustment. But, when writing to Reg 0 there's invariably a lock detect glitch of ~12µs (even with the requisite disabling of the VCO auto-cal and of ΣΔ reset).
Is there any workaround to prevent lock detect from glitching while a phase adjustment is made?
I think this will be difficult, as our lock detect circuit operates by comparing the phases from the reference and feedback paths to the PFD. So changing the phase at the Sigma Delta will change the phase, which may trigger a loss of lock.It would be interesting to know if a change to SD in which the phase only changes by a small amount triggers a loss of lock detect, it's probably wise to increase the LD window to it's highest window setting. I'll see if I can figure something out in the lab.
Thanks, this confirms my understanding of how it works (following some more consideration). I think we can say the architecture doesn't use a distinct phase control loop, such that if frequency was spot on but 180` out-of-phase the loop would not have a mechanism to simply adjust the phase but would nudge the frequency off center momentarily to realign phase, and the speed of this would be limited by the loop filter.
I tried making single-LSB phase changes in the lab already, with the idea that if it can keep lock then a large phase change could be made with multiple small adjustments of phase. But I found that LD always triggers. Still, it could be helpful to quantify the output disturbance.
Our findings are that a loss of lock event cannot be avoided when phase is adjusted. This is generally the case for VCO/PLLs that use the architecture wherein phase is adjusted within the frequency control loop - specifically in the ΣΔ modulator. Devoted phase delay circuitry is required to adjust the phase without affecting frequency lock, such as used in the multi-output clock gen & distribution parts HMC7044 & LTC6952.
I set this up in the lab, and any adjustment to phase disturbs the lock detect circuit.