ADF 5356 not locking with CE usage, lock is present when CE connected to VCC

ADF 5356 not locking with CE usage, lock is present when CE connected to VCC

During development we have changed the setup of the ADF 5356 from CE connected to Vcc to CE connected to CPU.

The 3.3 volt is present but there is no digital lock any more with the same code

As a test we have recreated the 3.3v directly to the CE pin and the lock is there again.

We have tried time delays(1 sec.) between turning the CE to a logic high and sending the data.

Please advice how to solve this problem.

Below is the settings in  the software.

// Value of the registers according the ADF5356 Evaluation board control software for 6600 MHz output with the changes for our board

// Register 0
// Bit 0 - 3: register number
// Bit 4 - 19: INT
// Bit 20: Prescaler 4/5 or 8/9
// Bit 21: Autocal -> 1
// Bit 22 - 31: Reserved -> 000000000
0x00300A20,

// Register 1
// Bit 0 - 3: register number
// Bit 4 - 27: FRAC1
// Bit 28 - 31: reserved -> 0000
0x0F684BD1,

// Register 2
// Bit 0 - 3: register number
// Bit 4 - 17: MOD2 LSB
// Bit 18 - 31: FRAC2_LSB
0x004401B2,

// Register 3
// Bit 0 - 3: register number
// Bit 4 - 27: Phase
// Bit 28: Phase adjust
// Bit 29: Phase resync
// Bit 30: SDload reset
// Bit 31: reserved -> 0
0x00000003,

// Register 4
// Bit 0 - 3: register number
// Bit 4: Counter reset
// Bit 5: Charge pump three state --> normal operation
// Bit 6: Powerdown
// Bit 7: Phase detector polarity
// Bit 8: Mux logic
// Bit 9: Ref mode
// Bit 10 - 13: Charge pump current --> 0,90
// Bit 14: Double buffer --> enabled
// Bit 15 - 24: 10 bit R counter
// Bit 25 Reference divide by 2 --> enabled
// Bit 26 Reference doubler
// Bit 27 - 29: Mux out --> Digital lock detect
// Bit 30 - 31: reserved -> 00
0x32014B84,
//0x22014B84,
//0x1A014B84,
//0x1A014984,

// Register 5
// Bit 0 - 3: register number
// Bit 4 - 31: reserved -> 0x00800025
0x00800025,

// Register 6
// Bit 0 - 3: register number
// Bit 4 - 5: RF output A power --> Max, During debuggen changed to -4 dBm instead of 5 dBm
// Bit 6: RF output A enable --> Enabled
// Bit 7 - 9: Reserved -> 000
// Bit 10: RF output B enable --> Enable
// Bit 11: Mute till lock detect --> Disabled
// Bit 12: reserved -> 0
// Bit 13 - 20: charge pump bleed current --> as low as possible
// Bit 21 - 23: RF divider --> 1
// Bit 24: Feedback select -> Divided
// Bit 25 - 28: reserved -> 1010
// Bit 29: Negative bleed --> Disabled
// Bit 30 Gated bleed --> Disabled
// Bit 31 Bleed polarity --> positive
0x95000476,


// Register 7
// Bit 0 - 3: register number
// Bit 4: lock detect mode --> Fractional
// Bit 5 - 6: Fractional lock detect precision --> 12 ns
// Bit 7: Loss of lock mode --> Enabled
// Bit 8 - 9: Lock detect cycle count
// Bit 10 - 24: reserved -> 000000000000000
// Bit 25: LE Sync --> Enabled
// Bit 26: reserved -> 1
// Bit 27: LE Sel Syn edge
// 28 - 31: reserved -> 0000
0x060000E7,

// Register 8
// Bit 0 - 3: register number
// Bit 4 - 31: reserved -> 0x15596568
0x15596568,

// Register 9
// Bit 0 - 3: register number
// Bit 4 - 8: Synthesizer lock timeout
// Bit 9 - 13: automatic level calibration timeout
// Bit 14 - 23: Timeout
// Bit 24 - 31: VCO band division --> 51
0x33113CC9,

// Register 10
// Bit 0 - 3: register number
// Bit 4: ADC --> Enabled
// Bit 5: ADC conversion --> Enabled
// Bit 6 - 13: ADC clock divider --> 202
// Bit 14 - 31: reserved -> 000000001100000000
0x00C032BA,

// Register 11
// Bit 0 - 3: register number
// Bit 4 - 23: reserved -> 01100001001000000000
// Bit 24: VCO band hold --> Disabled
// Bit 25 - 31: reserved -> 0000000
0x0061200B,

// Register 12
// Bit 0 - 3: register number
// Bit 4 - 11: reserved -> 01011111
// Bit 5 - 31 phase resync clock value
0x000015FC,

// Register 13
// Bit 0 - 3: register number
// Bit 4 - 17: MOD2 MSB
// Bit 18 - 31: FRAC2 MSB
0x0000000D