We are using your PLL part: LTC6948IUFD-4 with 30.72MHz clock reference to generate our RF frequency from 5.6GHz to 6.35GHz range.
We have used RFSimPLL latest version to check the output phase noise values based on reference phase noise. Also we have used your datasheet/EVB recommended Loop filter values.When we test in our board we observed expected phase noise values are not met from 100Hz to 100KHz offsets. We have LTC6948IUFD-4 eval-board with us and with that we have tested the same with very low phase noise signal generator for reference clock of 30.72MHz. We seen similar performance only without major improvements in eval-board.Then we have tried with same signal generator at 100MHz as reference clock and generated 6GHz and measured phase noise. We have seen huge phase noise improvements in 100MHz reference clock compared to 30.72MHz clock. We have attached both clock PN test results in your eval-board for your reference. Please check the same performance comparison with different clocks (30.72MHz & 100MHz) at your end and suggest a solution to improve the phase noise performance with 30.72MHz CLK.If possible please share the generated "Register content file" for our testing and verification.
Also Please find our PLL registers values attached for different clock used for your reference.
Did you update the loop filter for the new reference. I've attached a few documents, The first one show how to design the register settings and loop filter with FracNwizard. The second discusses selecting a good reference. The third one discusses the phase noise limitations of spectrum analyzers. Let me know if this helps.
Thanks your application notes.
Can you please suggest or send PLL registers for 30.72MHz clock with better phase noise, without short phase jumps
For the 30.72M settings, please make sure the BD>24 (i.e. reg 04, 0x38). This will improve the quality of the VCO calibration, over the reg04=0x8, which was too fast.
The default on-board loop filter was designed for a Fpfd=50M in fractional mode. When ever the Fpfd changes you will need to design a new loop filter. Below I provided before and after pictures of both your (Fractional, pfd=30.72M) and (Integer, pfd=100M) with the default loop filter vs optimized loop filters. The loop filter values for each plot are shown in the bottom left. Also, notice the in-band noise will increase as pfd decreases, this has to do with larger N-divider values. The reason for this is described in the datasheet.
PLL New Loop filter design files and REG values.zip
As per you suggestion we have implemented a new Loop filter for our Reference input of 30.72MHz and design files and results are attached for your verification.
(Due to better phase noise requirement we have designed a Loop filter with 11.2mA instead of 5.6mA for your reference and 10uH inductor is fixed in our design due to unavailability of default suggested values)
We are using your PLL to generate LO frequency around 6GHz for our OFDM (64-QAM) Transceiver application.
Where we are facing ALC calibration jumps which disturbs our frequency error window and degrade our system performance.
I have attached the register details for 6150MHz and design files and loop filter values updated in the same files.
During Register write to PLL from address 0x01 to 0x0D we followed the attached registers (OMUTE Enabled) and then we have written in address 0x0A (Value 0x01) to enable VCO CAL as per your Driver provided.
Also We have disabled OMUTE by Writing in address 0x02 (Value 0x00) at final.
Now we have verified our Transmission and Reception with your PLL and its working fine. But in this register write configuration without enabling ALC Calibration we have ALCLO bit was set "1" during read-back in regsiter 0x00.
If we enable ALCEN or ALCCAL or ALCULOK bits at initial the VCO frequency jumps are occurring which affect our system performance.
Now our Question is listed below,
1. How to do the ALC Calibration without affecting output Frequency jumps during operation, If PLL settling time is less than 200uS is also no issue for us?
2. If we proceed without ALC Calibration for our frequency range of 5.6GHz to 6.35GHz frequency range which need to be configured frequently during our operation, Will PLL provide stable performance for whole frequency range changes without loosing lock even from -20 to +85deg Celsius temperatures?
3. Is there any other register configurations or sequence which we are missing to get optimum performance?
Please check and suggest a solution to resolve the above issue.
It sounds like you should set ALCCAL=1, and then set the other ALC bits mentioned to 0. Performance should hold over the temperature range. This will provide an ALC calibration at each frequency change.
Also, I recommend loop filter with Icp=5.6mA. In practice we have not see the performance improvement with the 11.2mA setting and you will save some power. With that being said your 11.2mA loop filter looks like a good design and can be used.
But even setting ALCCAL bit alone also have the same issue.
1. Do I need to mute the RF output power must during any frequency changes?
2. Is it CAL bit to set again after writing all registers even after enabling AUTOCAL?
3. Will it help if I reduce my 4th order loop filter design to 3rd or 2nd order?
4. Can you specify what could be the maximum VCO jump (Freq) & duration expected during ALC Calibration?
If only ALCCAL is select, the ALC will operate during the VCO calibration process. So once the VCO calibration is complete, you shouldn't see any frequency changes due to the ALC calibration. But it sounds like you are seeing frequency changes after the VCO calibration process with ALCCAL=1, ALCEN=0, ALCMON=0 and ALCULOK=0. If this is true I believe this points to something else causing the frequency jumps. I'll get to this, but want to answer your 4 questions first.
1. Do I need to mute the RF output power must during any frequency changes? Either way can be ok. There a lot of narrow band VCOs in the LTC6948. The calibration process steps through several of these VCOs to find the best one for your frequency. While performing a VCO calibration and MUTE=0, you will see a wide range of output frequencies from the VCO selection process. This maybe ok for your application, but I prefer MUTE=1, as I'd rather the output off and not have to see all these odd frequencies show up.
2. Is it CAL bit to set again after writing all registers even after enabling AUTOCAL? AUTOCAL forces a calibration anytime one of the RD, ND or NFRAC registers are changed. With a fixed reference frequency, you will not need to program CAL if AUTOCAL is enabled. (note: some people have a variable reference frequency and in this case they would need to set CAL=1, as the LTC6948 AUTOCAL would not be able to recognize a change to the external reference frequency)
3. Will it help if I reduce my 4th order loop filter design to 3rd or 2nd order? It shouldn't
4. Can you specify what could be the maximum VCO jump (Freq) & duration expected during ALC Calibration? Lets not go this direction yet. I want to rule out something else first.
If the ALC is off. It shouldn't be causing a frequency jump. There is a chance your capacitor selection in your loop filter is causing an issue, or your reference is drifting slightly. What part number are you using for your reference?
Most likely what I think is going on is you may be seeing some micro-phonics from the capacitors in your loop filter? One way to test this out is to tap your board and see if your frequency is jumping. The tap will cause a vibration. If this is what is going on, you will need to change your loop filter to use only NP0/ or C0G capacitors as these are not susceptible to micro-phonics. Other surface mount capacitors like X7R or X5R are susceptible to micro-phonics. There are also these other capacitors that are called soft termination or flexiterm capacitors, that have made the X7R/X5R capacitors less susceptible to micro-phonics - however, they still have this issue (just to a lesser degree.)
With crystal oscillators I've also seen these are susceptible to vibrations. One cheap trick I use in lab to debug if this is where the frequency jump is coming from is to place the crystal oscillator board on top of bubble wrap. You can also place your LTC6948 demo board on top of bubble wrap and that may reduce the vibrations causing the micro-phonic issue - if that is what your are seeing. Its not a perfect experiment, but it may give us a clue.
Thanks for your detailed response.
There is one change in our register configuration. Addition to ALCCAL=1 bit enabled, we have also enabled ALCMON=1 to monitor ALCHI & ALCLO Flag status in 0x00 Register. Still we are observing frequency jumps in our final receiver decoder.
1.Will it ALCMON=1 bit will also cause VCO frequency jumps?
Also we have disabled ALCCAL=0 and enabled only ALCMON=1 to monitor ALCHI & ALCLO Flag status in 0x00 Register. We are always observe 0x0C (ALCLO SET) read back value in 0x00 register and due to ALCCAL bit disabled, Still rare frequency jumps observed in our receiver decoder.
2. Can we do it register write sequence like below,
During initial frequency write sequence from 0x06 to 0x0A we will keep disabled all ALC Calibration bits, then after all Write over and VCO Calibration time (20uS) we will enable ALCEN=1 to do ALC Calibration. Then after some time ALC Calibration completeted then we will disable ALCEN=0. But to do the same we need maximum ALC Calibration time to enable and then disable. If we do it ALC Calibration like above, will it work over operating temperature range?
The PLL total settling time <250uS with ALC Calibration okay for our application. Please check and confirm.
We have verified our reference oscillator is not having any issues or short jumps and part number is SiT5356(0.1ppm TCXO). Also we have given our TCXO output to some other PLL (HMC834) and with that PLL output we are not seeing any frequency jumps. By that way our TCXO confirmed.
we are using our product in table top without any micro vibration and used good quality mil grade capacitor only for your reference.
We are PLL for our software defined radio product where frequency hopping with OFDM signal is must for your information.
Also our OFDM signal is more sensitive to frequency jumps which lead to very high phase disturbance for our phase modulations.
Please check and suggest a solution to resolve the issue.