We are using your PLL part: LTC6948IUFD-4 with 30.72MHz clock reference to generate our RF frequency from 5.6GHz to 6.35GHz range.
We have used RFSimPLL latest version to check the output phase noise values based on reference phase noise. Also we have used your datasheet/EVB recommended Loop filter values.When we test in our board we observed expected phase noise values are not met from 100Hz to 100KHz offsets. We have LTC6948IUFD-4 eval-board with us and with that we have tested the same with very low phase noise signal generator for reference clock of 30.72MHz. We seen similar performance only without major improvements in eval-board.Then we have tried with same signal generator at 100MHz as reference clock and generated 6GHz and measured phase noise. We have seen huge phase noise improvements in 100MHz reference clock compared to 30.72MHz clock. We have attached both clock PN test results in your eval-board for your reference. Please check the same performance comparison with different clocks (30.72MHz & 100MHz) at your end and suggest a solution to improve the phase noise performance with 30.72MHz CLK.If possible please share the generated "Register content file" for our testing and verification.
Also Please find our PLL registers values attached for different clock used for your reference.
Did you update the loop filter for the new reference. I've attached a few documents, The first one show how to design the register settings and loop filter with FracNwizard. The second discusses selecting a good reference. The third one discusses the phase noise limitations of spectrum analyzers. Let me know if this helps.
Thanks your application notes.
Can you please suggest or send PLL registers for 30.72MHz clock with better phase noise, without short phase jumps
For the 30.72M settings, please make sure the BD>24 (i.e. reg 04, 0x38). This will improve the quality of the VCO calibration, over the reg04=0x8, which was too fast.
The default on-board loop filter was designed for a Fpfd=50M in fractional mode. When ever the Fpfd changes you will need to design a new loop filter. Below I provided before and after pictures of both your (Fractional, pfd=30.72M) and (Integer, pfd=100M) with the default loop filter vs optimized loop filters. The loop filter values for each plot are shown in the bottom left. Also, notice the in-band noise will increase as pfd decreases, this has to do with larger N-divider values. The reason for this is described in the datasheet.