LTC6948IUFD-4 Phase noise degraded with 30.72MHz Reference clock

We are using your PLL part: LTC6948IUFD-4 with 30.72MHz clock reference to generate our RF frequency from 5.6GHz to 6.35GHz range.


We have used RFSimPLL latest version to check the output phase noise values based on reference phase noise. Also we have used your datasheet/EVB recommended Loop filter values.
When we test in our board we observed expected phase noise values are not met from 100Hz to 100KHz offsets.

We have LTC6948IUFD-4 eval-board with us and with that we have tested the same with very low phase noise signal generator for reference clock of 30.72MHz. We seen similar performance only without major improvements in eval-board.

Then we have tried with same signal generator at 100MHz as reference clock and generated 6GHz and measured phase noise.  We have seen huge phase noise improvements in 100MHz reference clock compared to 30.72MHz clock.  We have attached both clock PN test results in your eval-board for your reference.

Please check the same performance comparison with different clocks (30.72MHz & 100MHz) at your end and suggest a solution to improve the phase noise performance with 30.72MHz CLK.

If possible please share the generated "Register content file" for our testing and verification.

Also Please find our PLL registers values attached for different clock used for your reference.

6G_Output_100M_CLK.txt
Addr	Data
0	0
1	4
2	0
3	1
4	78
5	0
6	8
7	3c
8	0
9	0
0a	10
0b	19
0c	0f
0d	0
0e	4
0a	11
6G_Output_30.72M_CLK.txt
Addr	Data
0	4
1	4
2	0
3	0
4	8
5	0
6	8
7	c3
8	14
9	0
A	0
B	39
C	4f
D	0
E	24
A	1

30.72Mhz Clock



PLL Registers updated
[edited by: sugu89 at 3:41 PM (GMT 0) on 13 Aug 2019]