We are using your PLL part: LTC6948IUFD-4 with 30.72MHz clock reference to generate our RF frequency from 5.6GHz to 6.35GHz range.
We have used RFSimPLL latest version to check the output phase noise values based on reference phase noise. Also we have used your datasheet/EVB recommended Loop filter values.When we test in our board we observed expected phase noise values are not met from 100Hz to 100KHz offsets. We have LTC6948IUFD-4 eval-board with us and with that we have tested the same with very low phase noise signal generator for reference clock of 30.72MHz. We seen similar performance only without major improvements in eval-board.Then we have tried with same signal generator at 100MHz as reference clock and generated 6GHz and measured phase noise. We have seen huge phase noise improvements in 100MHz reference clock compared to 30.72MHz clock. We have attached both clock PN test results in your eval-board for your reference. Please check the same performance comparison with different clocks (30.72MHz & 100MHz) at your end and suggest a solution to improve the phase noise performance with 30.72MHz CLK.If possible please share the generated "Register content file" for our testing and verification.
Also Please find our PLL registers values attached for different clock used for your reference.
Did you update the loop filter for the new reference. I've attached a few documents, The first one show how to design the register settings and loop filter with FracNwizard. The second discusses selecting a good reference. The third one discusses the phase noise limitations of spectrum analyzers. Let me know if this helps.
Thanks your application notes.
Can you please suggest or send PLL registers for 30.72MHz clock with better phase noise, without short phase jumps
For the 30.72M settings, please make sure the BD>24 (i.e. reg 04, 0x38). This will improve the quality of the VCO calibration, over the reg04=0x8, which was too fast.
The default on-board loop filter was designed for a Fpfd=50M in fractional mode. When ever the Fpfd changes you will need to design a new loop filter. Below I provided before and after pictures of both your (Fractional, pfd=30.72M) and (Integer, pfd=100M) with the default loop filter vs optimized loop filters. The loop filter values for each plot are shown in the bottom left. Also, notice the in-band noise will increase as pfd decreases, this has to do with larger N-divider values. The reason for this is described in the datasheet.
PLL New Loop filter design files and REG values.zip
As per you suggestion we have implemented a new Loop filter for our Reference input of 30.72MHz and design files and results are attached for your verification.
(Due to better phase noise requirement we have designed a Loop filter with 11.2mA instead of 5.6mA for your reference and 10uH inductor is fixed in our design due to unavailability of default suggested values)
We are using your PLL to generate LO frequency around 6GHz for our OFDM (64-QAM) Transceiver application.
Where we are facing ALC calibration jumps which disturbs our frequency error window and degrade our system performance.
I have attached the register details for 6150MHz and design files and loop filter values updated in the same files.
During Register write to PLL from address 0x01 to 0x0D we followed the attached registers (OMUTE Enabled) and then we have written in address 0x0A (Value 0x01) to enable VCO CAL as per your Driver provided.
Also We have disabled OMUTE by Writing in address 0x02 (Value 0x00) at final.
Now we have verified our Transmission and Reception with your PLL and its working fine. But in this register write configuration without enabling ALC Calibration we have ALCLO bit was set "1" during read-back in regsiter 0x00.
If we enable ALCEN or ALCCAL or ALCULOK bits at initial the VCO frequency jumps are occurring which affect our system performance.
Now our Question is listed below,
1. How to do the ALC Calibration without affecting output Frequency jumps during operation, If PLL settling time is less than 200uS is also no issue for us?
2. If we proceed without ALC Calibration for our frequency range of 5.6GHz to 6.35GHz frequency range which need to be configured frequently during our operation, Will PLL provide stable performance for whole frequency range changes without loosing lock even from -20 to +85deg Celsius temperatures?
3. Is there any other register configurations or sequence which we are missing to get optimum performance?
Please check and suggest a solution to resolve the above issue.
It sounds like you should set ALCCAL=1, and then set the other ALC bits mentioned to 0. Performance should hold over the temperature range. This will provide an ALC calibration at each frequency change.
Also, I recommend loop filter with Icp=5.6mA. In practice we have not see the performance improvement with the 11.2mA setting and you will save some power. With that being said your 11.2mA loop filter looks like a good design and can be used.