We config the HMC767 register like this:
REG 1 2REG 2 1REG 5 50F1CDREG 6 1D3FREG 7 304865REG 8 16FFFREG 9 3264REG B 1E061REG E 1REG F 81REG 3 AB
the REFCLK is 50MHZ, we want to get the 8.55GHZ signal output, but the PLL not locked.
I need your advice , thank you!
Please refer to the functional diagram shown in the datasheet.
1) For an 8.55 GHz output, the input to the internal PS will come from RFOUT/2 on the VCO so it will be at 4.275 GHz. Since RFOUT is greater than 8.0GHz (or input to internal PS is greater than 4.0GHz), the internal prescaler must be set to 'divide-by-2' so REG 0x08 =1. You currently have this bit set low.
2) Once the internal prescaler is enabled, the frequency will be divided down again yielding 2.1375 GHz at the input of the phase detector. Dividing 2.1375 GHz by 50 MHz results in N = 42.75. Your register file does not list REG 0x04 which is required and should be the last write instead of REG 0x03 since it is operating in fractional mode. REG 0x03 would be last if operating in INT mode.
3) REG 0x0B is also set improperly. This part requires an active loop filter so REG 0x0B  should be set.
4) Please consult the operating guide for the HMC767 which is available on analog.com and update the other registers as necessary. Be sure to verify the CP current setting and LD window settings.
Thank you for your advice! It's helpful for me.
Now the HMC767 has been locked, but there is another problem. Whatever data I config the reg03 ,the output is 8.03GHZ.
Can you give me some advice about this?
Now the problem is：
1.When we detect the lock signal from register 12h and the LD pin, the output is fixed to 8GHZ,and can't be changed.
2.When the output RF is right, we can't get the lock signal;
We need your help for this, thank you!
This is likely due to error in your reference frequency and / or lack of synchronization between the reference on your HMC767 eval board (if using the eval board) and your test equipment.
Sorry, I don't understand our question. You must reprogram the registers to change the frequency. Reg 0x03 is written last for INT mode and Reg 0x04 is written last in FRAC mode.