Hi, I would like to use HMC574A.
So, I have a question. Please help me.
I am experimenting with an evaluation board.
The A and B terminals of the HMC 574A, I think that the logic level needs to be different at every timing.First of all is this idea correct?
Take the evaluation board as an example.If you connect the A / B terminal before and after the inverter pass by 74 IC,
I think that there is a moment when the A / B terminal becomes the same logic level in nanosecond order.
①What is the state of the RF switch when the A / B terminals are at the same logic level?
②Are there any restrictions on using time when the A and B terminals are at the same logic level?
The HMC574A cannot be used to carry DC pulse waveform. The RF ports are internally biased close to high control voltage (i.e. 5V) so the part requires DC blocking capacitors that will prevent the operation…
The RF paths of HMC574A switch will be in undefined state (neither isolation nor insertion loss) and the RF ports will be will have poor return losses when A=B=low and A=B=high not shown in the truth table.
The s-parameter data measured at these undefined states is included in zipped s-parameter file available on the product web page.
We don't recommend to continuously bias HMC574A in undefined state when the RF input signal is applied. However there would be no issue due to being in undefined state for a short period of time in ns order during switching.
What is the maximum the RF input power applied to HMC574A? What is minimum application frequency?
Thank you for your answer.
For the minimum frequency, the pulse waveform is used this time.Therefore, it is not a single frequency.⇒ About DC-30MHz is assumed.
We want to use the maximum power up to the limit of “HMC574A”.This is because we want to handle high voltage pulses as much as possible.
Please let me know if there are any other design considerations.
The HMC574A cannot be used to carry DC pulse waveform. The RF ports are internally biased close to high control voltage (i.e. 5V) so the part requires DC blocking capacitors that will prevent the operation at DC.